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The Linux Kernel Is Preparing To Enable 5-Level Paging By Default
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On the surface this sounds like absolute insanity. We are talking about 64 bit processors here, why would you need more than two levels of paging. Maybe I’m missing something (totally possible) but with the two address ranges, virtual and hardware it would seem like the goal should have been to reduce the number of paving levels.
This is makes me wonder how this impacts ARM and Power. Makes me wonder if there is a good web site that goes into comparing addressing in the physical and virtual worlds for these processors.
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Yo Dawg I heard you like paging so I put some paging in your paging so you can page while you page
Would someone tell me how this happened? We were the fucking vanguard of shaving in this country. The Gillette Mach3 was the razor to own. Then the other guy came out with a three-blade razor. Were we scared? Hell, no. Because we hit back with a little thing called the Mach3Turbo. That's three blades and an aloe strip. For moisture. But you know what happened next? Shut up, I'm telling you what happened—the bastards went to four blades. Now we're standing around with our cocks in our hands, selling three blades and a strip. Moisture or no, suddenly we're the chumps. Well, fuck it. We're going to five blades.
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The Linux Kernel Is Preparing To Enable 5-Level Paging By Default
Phoronix: The Linux Kernel Is Preparing To Enable 5-Level Paging By Default
While Intel CPUs aren't shipping with 5-level paging support, they are expected to be soon and distribution kernels are preparing to enable the kernel's functionality for this feature to extend the addressable memory supported. With that, the mainline kernel is also looking at flipping on 5-level paging by default for its default kernel configuration...
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