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The Linux Kernel Is Preparing To Enable 5-Level Paging By Default

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  • The Linux Kernel Is Preparing To Enable 5-Level Paging By Default

    Phoronix: The Linux Kernel Is Preparing To Enable 5-Level Paging By Default

    While Intel CPUs aren't shipping with 5-level paging support, they are expected to be soon and distribution kernels are preparing to enable the kernel's functionality for this feature to extend the addressable memory supported. With that, the mainline kernel is also looking at flipping on 5-level paging by default for its default kernel configuration...

    http://www.phoronix.com/scan.php?pag...LVL-Paging-Def

  • #2
    [insert xkcd joke]

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    • #3
      Yo Dawg I heard you like paging so I put some paging in your paging so you can page while you page
      Would someone tell me how this happened? We were the fucking vanguard of shaving in this country. The Gillette Mach3 was the razor to own. Then the other guy came out with a three-blade razor. Were we scared? Hell, no. Because we hit back with a little thing called the Mach3Turbo. That's three blades and an aloe strip. For moisture. But you know what happened next? Shut up, I'm telling you what happened—the bastards went to four blades. Now we're standing around with our cocks in our hands, selling three blades and a strip. Moisture or no, suddenly we're the chumps. Well, fuck it. We're going to five blades.

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      • #4
        On the surface this sounds like absolute insanity. We are talking about 64 bit processors here, why would you need more than two levels of paging. Maybe I’m missing something (totally possible) but with the two address ranges, virtual and hardware it would seem like the goal should have been to reduce the number of paving levels.

        This is makes me wonder how this impacts ARM and Power. Makes me wonder if there is a good web site that goes into comparing addressing in the physical and virtual worlds for these processors.

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        • #5
          Data is getting bigger and bigger. Some servers have Terabytes of RAM.

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          • #6
            Originally posted by wizard69 View Post
            We are talking about 64 bit processors here, why would you need more than two levels of paging. Maybe I’m missing something (totally possible) but with the two address ranges, virtual and hardware it would seem like the goal should have been to reduce the number of paving levels.
            You REALLY should google what paging is for.

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            • #7
              Originally posted by wizard69 View Post
              We are talking about 64 bit processors here, why would you need more than two levels of paging. Maybe I’m missing something (totally possible) but with the two address ranges, virtual and hardware it would seem like the goal should have been to reduce the number of paving levels.
              Issue that 64 bit space is so huge that if you try to map it directly our with only few levels page table itself will eat up all your memory and much more.

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              • #8
                Originally posted by AsuMagic View Post
                [insert xkcd joke]
                Ah yes, the joke where people simultaneously think that core kernel scalability work is unimportant/not used, and that linux kernel developers had any role in Adobe flash support.

                Originally posted by wizard69 View Post
                On the surface this sounds like absolute insanity. We are talking about 64 bit processors here, why would you need more than two levels of paging.
                So you're not going to even bother searching online as to why operating systems have multiple levels of paging, and instead you're going to assume that the kernel developers are simply misguided or insane?
                Last edited by Space Heater; 09-14-2019, 02:56 PM.

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                • #9
                  This also smells like Zen 3 hbm/3D die stacking prep to me.

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                  • #10
                    Originally posted by Setif View Post
                    Data is getting bigger and bigger. Some servers have Terabytes of RAM.
                    I probably don't understand how OS paging works here, but why do we need to increase from 256 TiB limit, when today, Xeon can only do 768 GiB and EPYC can do 2 TiB per socket? How are we in jeopardy of hitting this 256 TiB limit today or in the near future?

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