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RISC-V's Linux Kernel Support Is Getting In Better Shape, Maturing On HiFive Unleashed

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  • RISC-V's Linux Kernel Support Is Getting In Better Shape, Maturing On HiFive Unleashed

    Phoronix: RISC-V's Linux Kernel Support Is Getting In Better Shape, Maturing On HiFive Unleashed

    The Linux kernel's RISC-V processor support is getting into good shape now since the support for this open-source processor ISA was originally introduced back for Linux 4.15. Moving forward, it's now expected the support to be maintained and only improve for the HiFive Unleashed developer board...

    http://www.phoronix.com/scan.php?pag...ISC-V-Maturing

  • #2
    Its nice to see this happening..
    On the Other side this board costs a lot of money, and mips boards out there, that chases OpenSource, costs less than half the price on that board..
    Hope that with time this boards will lower its price
    Last edited by tuxd3v; 08 March 2019, 11:03 AM. Reason: typos

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    • #3
      They could finally manufacture another batch of their microcontroller dev-boards, HiFive1. They’re not Linux-ready (they only have 16 kB of on-chip SRAM, which seems quite silly coupled with 16 MB of external flash memory for the program…), but they were somehow affordable ($59) devboards to play with the RISC-V hardware.

      They promised a refresh for Q1 2019. If they do and put a bit bigger (and perhaps external) RAM on it, with similar price tag, I might order it to play with RISC-V.
      Last edited by silmeth; 08 March 2019, 12:17 PM.

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      • #4
        Originally posted by silmeth View Post
        They could finally manufacture another batch of their microcontroller dev-boards, HiFive1. They’re not Linux-ready (they only have 16 kB of on-chip SRAM, which seems quite silly coupled with 16 MB of external flash memory for the program…), but they were somehow affordable ($59) devboards to play with the RISC-V hardware.

        They promised a refresh for Q1 2019. If they do and put a bit bigger (and perhaps external) RAM on it, with similar price tag, I might order it to play with RISC-V.
        The small RAM is mainly because it is alternately the D-cache - there is a bit to flip to make it work as either cache (of external RAM, on the SPI buses) or a flat 32k ram block, so that particular RAM isn't likely to change in size much.

        My main disappointment with the first gen of the chip was that they didn't bring out some of the (specifically needed for my application) silicon's functionality to external pins (I suspect was to cover some faults in that first-run silicon, by just not connecting those silicon pads out to pins - I doubt there was a cost issue between using a 48 vs 56/64 pin QFP package!).

        Also QSPI-0 (where the boot ROM lives) only works burst-more for READ operations (as far as I have been able to determine) which is fine for old-school boot-rom set-ups, but makes swapping in a small* QSPI F-RAM chip, for example, not a useful solution to adding a larger fast(ish) R/W ram space.

        *they go up to 1MBytes from Cypress, which is quite large for a micro-controller.
        ...

        What I'd really love is Micron to release something pin-compatible with one of their more popular SAMD chips with the AMD-M0+ swapped out for a similar-capabilty RV-32 core, and everything else largely identical!
        Last edited by LaeMing; 08 March 2019, 09:18 PM. Reason: Edit: make what I am expressing a bit less muddy!

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