Announcement

Collapse
No announcement yet.

AMD Zen 2 EDAC Support Being Readied, Preps For Up To 8 Memory Controllers Per Die

Collapse
X
  • Filter
  • Time
  • Show
Clear All
new posts

  • AMD Zen 2 EDAC Support Being Readied, Preps For Up To 8 Memory Controllers Per Die

    Phoronix: AMD Zen 2 EDAC Support Being Readied, Preps For Up To 8 Memory Controllers Per Die

    AMD developers continue working out the open-source enablement bits for Linux to handle the upcoming Zen 2 processors...

    http://www.phoronix.com/scan.php?pag...-30h-EDAC-Bits

  • #2
    Given that they're using separate CPU 'core' die (chiplets) and memory/IO die, the terminology in this comment could be taken to mean several things.

    Does it mean per chiplet or per I/O die? I'd guess it makes most sense to be per I/O die. But I'd be curious if anyone knows for sure.

    Comment


    • #3
      Originally posted by willmore View Post
      Given that they're using separate CPU 'core' die (chiplets) and memory/IO die, the terminology in this comment could be taken to mean several things.

      Does it mean per chiplet or per I/O die? I'd guess it makes most sense to be per I/O die. But I'd be curious if anyone knows for sure.
      It may be prediction of multigate RAM as well

      Comment


      • #4
        Originally posted by willmore View Post
        Given that they're using separate CPU 'core' die (chiplets) and memory/IO die, the terminology in this comment could be taken to mean several things.

        Does it mean per chiplet or per I/O die? I'd guess it makes most sense to be per I/O die. But I'd be curious if anyone knows for sure.
        That's the Rome I/O die. The Chiplets don't have memory controllers.

        Comment


        • #5
          "8 memory controllers per package" is probably better wording. As others already said, the chiplet dies don't have memory controllers at all.

          Comment


          • #6
            Originally posted by xorbe View Post
            "8 memory controllers per package" is probably better wording. As others already said, the chiplet dies don't have memory controllers at all.

            1st gen EPYC already had 8 memory channels per package, but they were split among the dies. so 8 controllers on a single I/O die is probably accurate when describing the 2nd gen Rome layout. Having all the Rome core chiplets route through the I/O die for main memory access will be a different NUMA layout compared to Naples where a DRAM access could be 0 hop (direct connected die), 1 hop (other die on package), or 2 hops (die on another package in 2 socket system).

            Comment


            • #7
              Any possibility that this could be too support HBM memory?

              There where brief runors about APU’s supporting HBM some time ago. Those rumors died but the fact remains APUs need lots of bandwidth.

              Comment

              Working...
              X