Announcement

Collapse
No announcement yet.

Western Digital To Open-Source The "SweRV" RISC-V Core In 2019

Collapse
X
 
  • Filter
  • Time
  • Show
Clear All
new posts

  • Western Digital To Open-Source The "SweRV" RISC-V Core In 2019

    Phoronix: Western Digital To Open-Source The "SweRV" RISC-V Core In 2019

    More than a year ago Western Digital talked up how they would begin designing RISC-V cores and shipping them in devices and that is indeed panning out. The company has unveiled their new SweRV core and plans to open-source it in 2019...

    Phoronix, Linux Hardware Reviews, Linux hardware benchmarks, Linux server benchmarks, Linux benchmarking, Desktop Linux, Linux performance, Open Source graphics, Linux How To, Ubuntu benchmarks, Ubuntu hardware, Phoronix Test Suite

  • #2
    > 32-bit, 2-way super-scalar design that features a 9-stage pipeline core and clocks up to 1.8GHz and manufactured on a 28nm process

    For reference, the first gen RasPi's BCM2835 SoC had an ARM11 v6 ARM1176JZF-S 32bit processor with an eight-stage pipeline, hardware floating point and SIMD support while clocking around 700MHz and being manufactured on a 65nm process. There was also a DSP folks were using for audio projects and the Jazelle DBX no one really cared about.

    Looking at these mighty specs, I guess next year is the year of the hard drive linux

    Comment


    • #3
      Wel yeah underwhelming if you are looking for an applications processor to replace an Intel chip. However there is still a lot of embedded 32 bit work going on and such a chip will appeal to some. The 28nm node does seem a bit old but I really wonder how much power management tech was put into their design.

      I guess the good thing here is that it will be an open design that actually ends up in hardware. Iā€™m not super motivated by open hardware myself but I do know others consider it to be attractive. Then again I donā€™t see much use for the chips that Western Digital will be making for the DIY PC crowd.

      I do wonder how quickly this IP will get designed into more open embedded controllers. It would be neat to see the Arduino community adapt this core design into a chip especially designed for that community. Iā€™m not sure much money would be saved but it would certainly do much for the communities focus on education.

      Of course a more general purpose chip from Western Digital for the Arduino community would work too. It makes me wonder if WD will move into the more general world of embedded processors like NXP and others.



      Originally posted by c117152 View Post
      > 32-bit, 2-way super-scalar design that features a 9-stage pipeline core and clocks up to 1.8GHz and manufactured on a 28nm process

      For reference, the first gen RasPi's BCM2835 SoC had an ARM11 v6 ARM1176JZF-S 32bit processor with an eight-stage pipeline, hardware floating point and SIMD support while clocking around 700MHz and being manufactured on a 65nm process. There was also a DSP folks were using for audio projects and the Jazelle DBX no one really cared about.

      Looking at these mighty specs, I guess next year is the year of the hard drive linux


      Comment


      • #4
        why use this instead of boom ? it has both 2 and way superscalar variants

        Comment


        • #5
          Company making hard drives and SSDs opensourcing a HDD/SSD controller, people on Phoronix forums complain and make dumb comparisons with a Raspi, which is a low-end embedded device SoC, and as such is on a completely different scale.

          Overall I'd say it's good. I wouldn't mind having FOSS firmware for a SSD eventually, and this is a step in the right direction.

          Comment


          • #6
            Originally posted by c117152 View Post
            > 32-bit, 2-way super-scalar design that features a 9-stage pipeline core and clocks up to 1.8GHz and manufactured on a 28nm process
            I hope it prediction would be in order, instead of out of order..
            With spectre and meltdown out there and side channel attacks...better play safe..

            For Microcontrollers, there are already a very good RISCV implementation, the Pulp Core.
            PULP platform is an open-source efficient RISC-V architecture.


            And for arduino like you already have SiFive Fe310, and the mighty GAP8( for CPU cluster computing..some sort of GPU computing but with CPUs, at a much lower power consumption ):
            https://greenwaves-technologies.com/...ion-processor/

            Compare the power Comsumption, with a STM32 F7:
            Last edited by tuxd3v; 05 December 2018, 10:47 AM.

            Comment


            • #7
              This is absolutely amazing! šŸ¤©

              An open source ISA on open source! ā¤šŸ‘

              Comment


              • #8
                Originally posted by GunpowaderGuy View Post
                why use this instead of boom ? it has both 2 and way superscalar variants
                Is it being implemented and use anywhere? Just wondering. Comparing to something that will be battle tested by Western Digital.

                Comment


                • #9
                  Does it run Crysis?

                  Comment


                  • #10
                    Originally posted by starshipeleven View Post
                    Company making hard drives and SSDs opensourcing a HDD/SSD controller, people on Phoronix forums complain and make dumb comparisons with a Raspi, which is a low-end embedded device SoC, and as such is on a completely different scale.
                    You are implying that HDD/SSD controllers are high-end processors. Well, everything is relative, but that comparison wasn't the worst.

                    Comment

                    Working...
                    X