I think, especially in the 128-bit field, that risc-v separates the instruction set address space. So yes, some implementations could include proprietary instructions, and we'd face a situation like ARM all over again, where you need precompiled kernels and custom initramfs, and what works for one ARM core doesn't work for another ARM core. Try to boot any ARM device with your own compiled distro, and see the headaches. I hope this doesn't happen to risc-v.
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The Linux Foundation Is Teaming Up With RISC-V To Promote The Open-Source CPU ISA
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Originally posted by Apokalypz View PostWould be nice to tinker with, but performance wise it has to compete with arm to be practical for people not into FOSS and (FOSH?) In current real world uses. Which brings me to a question: Does a free ISA mean a free implementation? I would imagine all the optimized logic bits would be developed by those with the means to which would likely patent the implementation. So, assuming an implementation can be closed with an open ISA, it will probably be a case where the performant implementations aren't free, but the slow ones are.
Right?
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Originally posted by computerquip View PostI have no clue if I should be interested or not as a general purpose developer. Is it wanting to be an alternative to x86? To ARM? I legit can't tell. It seems to be an open ISA that has no immediate goal other than being an ISA.
Not only is it a open ISA, but it is also a clean and modern ISA.
The first RISC-V chips are intended as alternatives to ARM Cortex-M and ARC for microcontroller use. Nvidia have their own implementation of RISC-V called Falcon that they use in their GeForce cards. Western Digital also use RISC-V for their microcontrollers in storage devices.
So initially RISC-V is being adopted for microcontrollers and can be used as an alternative to ARM Cortex-M and ARC.
Perhaps later when there are designs with more features and performance, it can be used as an alternative to ARM Cortex-A.
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