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OpenRISC Port Revised For GCC, Still Trying To Be Mainlined Soon

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  • OpenRISC Port Revised For GCC, Still Trying To Be Mainlined Soon

    Phoronix: OpenRISC Port Revised For GCC, Still Trying To Be Mainlined Soon

    The GCC steering committee decided earlier this year they will accept the OpenRISC port for this processor ISA while the patches for it are still being prepped...

    http://www.phoronix.com/scan.php?pag...SC-GCC-Port-V4

  • #2
    OpenRISC feels rather redundant now with RISC-V which seems to have a much bigger momentum, more players that back it, and an architecture designed by renowned people in the field.

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    • #3
      Originally posted by uid313 View Post
      OpenRISC feels rather redundant now with RISC-V which seems to have a much bigger momentum, more players that back it, and an architecture designed by renowned people in the field.
      It's still used as the supervisor processor in all Allwinner chips, so there's need for a modern compiler for it. It would be much nicer to have a current compiler for both the kernel and the ATF rather than having to keep two full toolchains of different versions.

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      • #4
        Originally posted by willmore View Post

        It's still used as the supervisor processor in all Allwinner chips, so there's need for a modern compiler for it. It would be much nicer to have a current compiler for both the kernel and the ATF rather than having to keep two full toolchains of different versions.
        Oh, I didn't know OpenRISC had any real world commercial use.

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        • #5
          Originally posted by uid313 View Post

          Oh, I didn't know OpenRISC had any real world commercial use.
          Nope, still in active use in millions of SoCs. Support for it is critical for these platforms to have advanced power management as the supervisor core can shut down the main ARM cores and power down other parts of the chip. If these devices are ever to have solid power management, then efforts like this to mainline support in GCC are helpful.

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          • #6
            Hmm, the core OpenRISC instruction set looks pretty nice, and it even has vector extensions unlike RISC-V. On the negative side, no compressed instructions and a silly branch delay slot feature that was outdated 20 year ago.
            Last edited by carewolf; 11-08-2018, 06:48 PM.

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            • #7
              Originally posted by carewolf View Post
              Hmm, the core OpenRISC instruction set looks pretty nice, and it even has vector extensions unlike RISC-V. On the negative side, no compressed instructions and a silly branch delay slot feature that was outdated 20 year ago.
              Yeah, while clever at the time and a fun feature of the R2000, it's not something you want to see in a modern arch. But, keep in mind that there's a place for everything and these cores aren't normally implemented as the main application processor, they're used as a supplimentary processor. Intel used them in their chipsets not too long ago to run the management engine. We're talking well sub GHz speeds.

              As far as code density goes, yeah, it's a bummer, but these cores are meant to be *small* on the die and any unnecessary stuff gets left out. I might even assert that if you're worried about code density with one of these, you're doing something wrong. Though, everyone has a different set of requirements.

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