SiFive Unleashes New 7-Series RISC-V Cores With Better Performance

[tildearrow]

Typo:

The new SiFive U74 cores are reported to be comparable to the ARM Cotex-A55,

[M@yeulC]

How is the perf/Watt, though? That's kind of the most important metric nowadays...

[Min1123]

So, I'm looking forward to the specs and tech related to the Blackbird PPC from RaptorCS because I want to replace my desktop web+dev computer with something open and unencumbered (as much as it can be at this point) and use my current desktop mostly for gaming. For me, for now that means using PPC64le + AMD GPU + Fedora (I like SELinux).

With this possibly getting power+performance of an ARM Cortex-A55, which is the successor to the ARM Cortex-A53 that is used in the Raspberry Pi 3 (I mention because it's popular and well-known), maybe I can get an RPi3 replacement out of this, which would be nice, but it doesn't get me to RISC-V + AMD GPU (or an open one?) + Fedora, which is where I'd actually like to be.

Maybe someone'll make a laptop, or a board I can stick in a PiTop using one of these chips.

[tuxd3v]

Without interesting price as Odroid C2, ... will never sell.
And I-Class I6500 Multiprocessor Core cheaper hardware?

The Mips64 is indeed a very good replacement for light Desktop Usage, much better than what ARM offers now..

"Up to four threads per core can be implemented, and up to six cores per cluster, and up to 64 clusters can be implemented together for a total of 384 cores and 1,536 threads."
up to 8 Mb cache L2, virtualization, offers no burden on context switchs!

Its a beast!!
I don't get why do one is creating a board with suficient specs for a Desktop Usage..sincerely.

[ldesnogu]

The Mips64 is indeed a very good replacement for light Desktop Usage, much better than what ARM offers now..

"Up to four threads per core can be implemented, and up to six cores per cluster, and up to 64 clusters can be implemented together for a total of 384 cores and 1,536 threads."
up to 8 Mb cache L2, virtualization, offers no burden on context switchs!

Its a beast!!
I don't get why do one is creating a board with suficient specs for a Desktop Usage..sincerely.

This is much slower than many ARM CPU for single thread tasks, I bet it's around Cortex-A53. And I'm not even sure anyone made a chip out of it.

[Dawn]

This is much slower than many ARM CPU for single thread tasks, I bet it's around Cortex-A53. And I'm not even sure anyone made a chip out of it.

Indeed. Dual-issue in-order.

[microcode]

The S7 is within 0.1 CoreMark/MHz of ARM's M7; both are dual-issue in-order (I think, SiFive doesn't exactly say), vs U54-MC which was single-issue. Before really comparing to Cortex-A on standard code, they'll probably need out-of-order. Other RISC-V vendors are working on out-of-order implementations, and we'll see what those accomplish in time.

As a matter of peak performance, you can accomplish that right now by just clocking the in-order implementations higher (and honestly not that much higher, all told).

[coder]

built on an optimized 8-stage in-order pipeline (to help with side channel attacks)

This is called spinning a weakness into a strength.

A better way to mitigate against side-channel attacks is to make a fast out-of-order core without SMT.

[microcode]

This is called spinning a weakness into a strength.

A better way to mitigate against side-channel attacks is to make a fast out-of-order core without SMT.

SMT is not required for speculation sidechannel attacks.

[coder]

SMT is not required for speculation sidechannel attacks.

Sure, but foregoing OoO isn't the only way to mitigate against them.

IMO, the obvious reason it's in-order is that it wasn't feasible for them to do OoO, either due to schedule or market constraints. It just bugs me to see that spun as the reason. Don't know if it was Michael's doing, or if that was their official line. Either way - not good.