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C-SKY Architecture Approved For The Linux Kernel, Might Be The Last New CPU Arch

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  • #11
    Originally posted by coder View Post
    At a high level, it smells a bit like Intel's EPIC. But, when you dig into it, I see more similarities with transport-triggered architectures.
    No idea. I'm not up to date and mostly forgot the hardware stuff. Looking it up, it was discussed over at the Mill forums: https://millcomputing.com/topic/micr...dge-processor/

    Originally posted by coder View Post
    According to the update in that Register article, I wouldn't hold my breath for it to see the light of day. But it's always good to know that the wheels of processor research are still turning.
    The article seems to have been issued in advance of a spree of patent approvals to prevent stock market speculations:
    https://patents.justia.com/patent/10095519 https://patents.justia.com/patent/20180267807 https://patents.justia.com/patent/10061584 etc...

    Assuming it works, commercialization is tricky since Microsoft can make it exclusive for the Azure cloud. Depends on the market conditions mostly.

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    • #12
      Originally posted by coder View Post
      Very cool. This might be something towards what I was talking about - reducing dependence on speculative execution and perhaps even the cache hierarchy.

      At a high level, it smells a bit like Intel's EPIC. But, when you dig into it, I see more similarities with transport-triggered architectures.

      According to the update in that Register article, I wouldn't hold my breath for it to see the light of day. But it's always good to know that the wheels of processor research are still turning.
      IA-64 didn't do any kind of speculative execution at all. It was a VLIW like architecture made for SIMD instructions. It actually executed every branch in full everytime. It's exactly why it sucked so bad at general purpose compute and why it sucked so bad at emulating x86. It would've been an absolutely horrible consumer product.

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      • #13
        Originally posted by duby229 View Post
        IA-64 didn't do any kind of speculative execution at all.
        Protip: try reading the article we're talking about. You might not waste time making irrelevant comments.

        The design of E2 is a radical departure from the computer chips designed by Intel, Arm, AMD, and others. It uses an instruction set architecture known as explicit data graph execution, aka EDGE
        Now, does that not sound a bit like EPIC? Intel's EPIC (Explicitly Parallel Instruction Computing) also explicitly encodes data dependencies.

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        • #14
          Originally posted by coder View Post
          Protip: try reading the article we're talking about. You might not waste time making irrelevant comments.


          Now, does that not sound a bit like EPIC? Intel's EPIC (Explicitly Parallel Instruction Computing) also explicitly encodes data dependencies.
          Here's a protip for you, Try to understand why I said what I said. I did read the article, but my response wasn't to the article it was to -you-.

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          • #15
            Originally posted by duby229 View Post
            my response wasn't to the article it was to -you-.
            Then here's a request: please don't try to school me on CPU architectures.

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            • #16
              Originally posted by coder View Post
              Yeah, it's silly to think that ISA design is at a dead end. With process-lead performance improvements hitting a wall, there's too much to be gained by rethinking the whole relationship with caches. Also, branch prediction efficiency might be improved with explicit hints. There are other sorts of innovations possible, I'm sure.
              I am sure this can be added to existing ISAs in a backward compatable fashion.

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              • #17
                Originally posted by jpg44 View Post
                I am sure this can be added to existing ISAs in a backward compatable fashion.
                It's not likely to see the memory consistency model of a given ISA change within its lifetime. That's the sort of thing which can seriously break backward compatibility, keeping CPU designers well away.

                For CPU designers desperate to squeeze a couple more % out of a design, cache is like a drug. They know adding it will improve performance, at a cost. So long as they're not too focused on power-efficiency, it's a temping way to spend transistor and power budget.

                Yet, a lot of times, software would be as happy with some fast, local memory. And there are times and places where some software-managed content-addressable memory would be quite useful. So, putting cache more directly under the control of software seems like an interesting avenue to explore.

                You're right that speculative execution could receive tweaks within existing ISAs. I'm imagining something like a "green light" that tells in advance when a branch is guaranteed to be taken. For power-optimized CPUs (or those running in low-power mode), this might be the only situation where it goes ahead, in order to minimize the chance of burning power only to discard a result, not to mention all the power needed to make a guess about which way to go.

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                • #18
                  Originally posted by c117152 View Post
                  Admittedly it's still behind closed doors, but Microsoft's E2 was being ported last I heard: https://www.theregister.co.uk/2018/0...ge_windows_10/
                  The circle is now almost complete. Who will be the next challenger when current devolves from a software house into a hybrid hardware/software provider that can try to block competition on their hardware?

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