AMD Threadripper 2000 Series Details: Up To 32-Cores / 64-Threads With The 2990WX

[phoronix]

Phoronix: AMD Threadripper 2000 Series Details: Up To 32-Cores / 64-Threads With The 2990WX

AMD's Threadripper 2990WX 32-core / 64-thread processor is real and launching next week. At the end of July we were in Maranello, Italy for AMD's Threadripper "2nd Gen" Tech Day, and while there have been leaks in recent days/weeks, today the embargo expires for being able to talk about this high-end desktop platform update.

http://www.phoronix.com/vr.php?view=26655

[boxie]

Hey, That's cool! All that work you have done on the AMD CPUs has really paid off! Hope you had fun at the briefing!

Can't wait for your review

[GruenSein]

Did they elaborate on the fact, that they will have two dies with direct dual channel memory access and two with memory access over IF? Giving each die a single memory channel so it will have access to low latency RAM could've made sense, too. Or is it simply because the previous generation had only two active dies and they did not want to redo the wiring to the socket?

[schmidtbag]

Did they elaborate on the fact, that they will have two dies with direct dual channel memory access and two with memory access over IF? Giving each die a single memory channel so it will have access to low latency RAM could've made sense, too. Or is it simply because the previous generation had only two active dies and they did not want to redo the wiring to the socket?

To my understanding, when it comes to the 2990WX, two of the dies have access to a pair of memory channels, the other two get their data through the Infinity Fabric. That being said, this will significantly hurt performance compared to the Epyc 7551P (at least when scaling for clock speed differences).

That being said, if the 2950X also has 4x active dies (I'm not sure if it does), I think it'll be a much slower product than the 1950X in many tests.

[metalliax]

That being said, if the 2950X also has 4x CCXs (I'm not sure if it does), I think it'll be a much slower product than the 1950X in many tests.

The 2950x and 1950x both have 4x CCX (2 active dies), so the 2950x performance should be equal/better than 1950x in every category. The 2990WX and 2970WX have 8x CCX.

[schmidtbag]

The 2950x and 1950x both have 4x CCX (2 active dies), so the 2950x performance should be equal/better than 1950x in every category. The 2990WX and 2970WX have 8x CCX.

My bad - I meant 4x active dies. But anyway, thanks for clarifying that the 2950X is 2 dies.

[discordian]

To my understanding, when it comes to the 2990WX, two of the dies have access to a pair of memory channels, the other two get their data through the Infinity Fabric. That being said, this will significantly hurt performance compared to the Epyc 7551P (at least when scaling for clock speed differences).

Yeah, I don't think NUMA can properly deal with that (for now atleast), it usually has to correlate memory areas to CPUs. Here you have 2 x 8 Cores with their attached RAM and 16 which always have (atleast) 1 hop.
To maximize system effciency those 16 cores should get the cache-affine, low memory bandwidth tasks. This classification is not done by NUMA.

[GruenSein]

To my understanding, when it comes to the 2990WX, two of the dies have access to a pair of memory channels, the other two get their data through the Infinity Fabric. That being said, this will significantly hurt performance compared to the Epyc 7551P (at least when scaling for clock speed differences).

That being said, if the 2950X also has 4x active dies (I'm not sure if it does), I think it'll be a much slower product than the 1950X in many tests.

I am well aware of that. I am simply wondering WHY this approach was chosen. My guess is still socket compatibility. Maybe, the dual channel interface of a single die shares a clock (or any) pin for both channels making it impossible to use four independent single channels on the same socket.

The current implementation could certainly benefit from a scheduler that is aware of the CCXs relative memory proximity. Not sure, how effective it could be at tracking the memory requirements in terms of bandwidth and latency. On the other hand: IF seems to have enough bandwidth to sustain full DRAM bandwidth. The main penalty is the increased latency (80ns local vs 120ns over IF or something IIRC).

[audir8]

It's all about trade-offs, spending $2k on a quad channel 32C/64T solution is entirely competitive with Intel and other AMD products. An extra hop to memory isn't the end of the world, It's essentially having higher CL RAM, until you're bandwidth starved, and at that point, you're essentially spending 2x as much to get more memory channels with the same amount of cores. If AMD didn't have CCXes, just making this trade-off would be impossible, and prices would be 1.5x to 2x on having more cores.

TR4 goes from 8C to 32C. AM4 from 4C to 8C. Will there be any overlap for those of us who don't want to deal with ECC RAM?

[ctlansdown]

In the 2950X, is the 4.4GHz turbo including XFR or before XFR?