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MIPS Rolls Out New I7200 Processor Core Using New nanoMIPS ISA

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  • Ardje
    replied
    Originally posted by elvenbone View Post
    So is this an architecture we might see in routers in the future?
    MIPS itself is a pretty long lived architecture.
    Any Broadcom NIC in a PC sports a sports a mip cpu, hence the backdoors in them. The older access points were mips based. But usualy a router/switch contained a coldfire or a mips.
    I even have 2 netbooks sporting a mips 8-D.
    But yeah, I guess, we might see some switch SoC's from broadcom.

    Leave a comment:


  • mfortune
    replied
    Originally posted by carewolf View Post
    Is there openly available documenation of the ISA somewhere?
    Architecture docs are here: https://www.mips.com/products/architectures/nanomips/
    Tools and software docs are here: https://codescape.mips.com/component...ps/2018.04-02/

    Leave a comment:


  • carewolf
    replied
    Is there openly available documenation of the ISA somewhere?

    Leave a comment:


  • mfortune
    replied
    Originally posted by microcode View Post
    I wonder how nanoMIPS compares to RVC in terms of compactness of large codebases like the Linux kernel, and the interrupt handlers more specifically. I'm guessing the 48-bit encoding is for MSA instructions, or maybe it's unused?
    I recommend trying out the comparison for yourself, grab a toolchain of your choice and see how it shapes up against nanoMIPS. You may well be surprised by the results; in fact, let's go all in and open up the comparison beyond just GCC. Just watch out for all the common pitfalls when doing code size analysis, every architecture comes with its own subtleties. To answer your question on 48-bit... the 48-bit instructions are quite focused and are all 'add' instructions with a 32-bit immediate including some carefully chosen implicit source registers to catch the set of common patterns. Think of it as part of a wider set of functionality that provides an alternative to constant pools that can be found in MIPS16e and other ISAs.

    Leave a comment:


  • DMJC
    replied
    There's always the hope that Moore's law slams into a solid brick wall and custom architectures become sexy again... Or not.

    Leave a comment:


  • discordian
    replied
    Originally posted by squash View Post
    MIPS is such an odd duck. They've been around for so long and have played in the ultra high end as well as the ultra low end.. But after splitting off PowerVR it seems like they're just steadily sinking. They're certainly not capturing hearts and minds the way ARM is, despite having a bunch of superior features. And maybe that's fine. Being an also-ran isn't bad if you're still shipping millions of units. RC Cola makes a lot of money even though everyone you know drinks Coke and Pepsi. And compared to many of their contemporairies (PA-RISC, Alpha) just existing in 2018 is an accomplishment.
    Well, they were steadily sinking since forever. Its really unfortunate as this was primary the fault of SGI (long time owner ) basically doing jack & shit with it. ARM focused on getting its cores everwhere and they eventually catched up with the Cortex-A8 and mostly copied everything with its 64bit architecture.
    Technically MIPS has alot less cruft then ARM, let alone x86 - it can support 32 and 64 with a single decoder (rare feat, RISC-V does this too), as 64bit is just a superset of instructions instead of a different encoding.

    but the core is just one part, if you dont have a big ecosystem of busses and peripherals, you have a stiff uphill battle. Now with RISC-V in the mix, I don't see any hope for the ISA.

    Leave a comment:


  • c117152
    replied
    Originally posted by elvenbone View Post
    So is this an architecture we might see in routers in the future?
    "high bandwidth modem subsystems in Advanced LTE Pro and upcoming 5G smartphone SoCs, as well as networking ICs, and other applications."

    So more like baseband or IoT.

    Leave a comment:


  • squash
    replied
    MIPS is such an odd duck. They've been around for so long and have played in the ultra high end as well as the ultra low end.. But after splitting off PowerVR it seems like they're just steadily sinking. They're certainly not capturing hearts and minds the way ARM is, despite having a bunch of superior features. And maybe that's fine. Being an also-ran isn't bad if you're still shipping millions of units. RC Cola makes a lot of money even though everyone you know drinks Coke and Pepsi. And compared to many of their contemporairies (PA-RISC, Alpha) just existing in 2018 is an accomplishment.

    But let's be honest. ARM is eating the bulk of their lunch. It's in every space they're in, and a bunch of spaces they aren't. It's accessible in ways MIPS just isn't.

    Getting started with ARM is as easy as grabbing a Raspberry Pi. https://amzn.to/2joI2Yi

    Need to go smaller? $18 on Amazon buys you a 2 pack of STM32 development boards and a USB programmer. https://amzn.to/2JOK4ft

    Need to go bigger? $500 on Amazon buys you a Tegra X1 development board. https://amzn.to/2FBByOc

    Need to go REALLY big? Cavium is one of several vendors producing huge ARM servers. https://www.anandtech.com/show/12571...thunderx2-socs

    Even with MIPS Creator series of hobbyist boards (several years old at this point) they're just not doing much to capture the attention of this generation of developers and systems builders.

    Leave a comment:


  • sykobee
    replied
    The ISA is assembly compatible, it's the instruction encoding that has changed for nanoMIPS.

    There's a 16-bit encoding for many common instructions, 8 registers and target register is source register type stuff. It's probably similar to the previous 16-bits MIPS compact ISA.
    Then there is a 32-bit encoding, 32 registers, I think this is standard MIPS in the main.
    Then there is a 48-bit encoding that crushes several instructions together (common instruction sequences), or is used for 32-bit immediates.

    The thing is, this is the only ISA supported, and the combination of 16-bit instructions and 48-bit crushed instruction sequences means the ISA is very compact now.

    Also the core has higher performance than ARM A53 and ARM R8, allegedly.

    Leave a comment:


  • microcode
    replied
    I wonder how nanoMIPS compares to RVC in terms of compactness of large codebases like the Linux kernel, and the interrupt handlers more specifically. I'm guessing the 48-bit encoding is for MSA instructions, or maybe it's unused?

    Leave a comment:

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