Originally posted by oiaohm
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PCI Express 7.0 Specification Announced - Hitting 128 GT/s In 2025
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Originally posted by torsionbar28 View PostNot disagreeing, but I understand why they do it. The x1 PCIe slots that is, not the hot dogs. Gen2 x1 has 500 MB/s of bandwidth. Not many consumer use cases need more than that. That's close to the SATA limit, which is good enough for the vast majority of consumers.
For those who need a little more, you can buy an Gen3 x8 SAS adapter for $50 used that gives you 8 SATA/SAS ports at full speed. Or something like Thunderbolt. I honestly cannot picture what kind of consumer use case there is for an x1 card that needs >500 MB/s of bandwidth.
Gen 4 1x slot = 1.969GBps
Gen 5 1x slot = 3.93GBps
I could think of a lot of use cases for a Gen 4 1X slot, even in consumer boards.
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Originally posted by cthart View PostNow the CPUs are playing catchup to the buses.
CXL memory is both a solution to this problem, as well as fueling it (i.e. with CXL leveraging the PHY layer of PCIe). In other words, if you put your memory out on the bus, as well, then you can presumably scale it in a way that's balanced against your system's overall needs. However, putting it on the bus means you now need ~double the aggregate bus bandwidth than before.
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Originally posted by commodore256 View PostI think this spec might be mostly be used for glue logic chiplets for accelerators
CCIX and CXL have tried to tackle the chiplet interconnect problem, but UCIe represents a more comprehensive framework for addressing it. It can use the existing PCIe and CXL protocols, without the baggage from their PHY specifications. It also supports implementation-specific custom protocols, so that someone like AMD could continue to use their Infinity Fabric interconnect between two of their chiplets, over a UCIe PHY layer.
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Originally posted by oiaohm View PostThere are a few consumer PCIe 5.0 ssd on the market. Yes M.2. More will come.
And no: consumers don't need (i.e. can't benefit from) PCIe 5.0 SSDs. There's plenty more headroom left in PCIe 4.0. Intel simply got embarrassed by AMD leap-frogging them on PCIe 4.0 and decided to turn the tables, in Alder Lake. There's no practical justification for what they did, but it certainly had the effect of pushing up prices of Alder Lake motherboards.
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Originally posted by tildearrow View PostI'm going to announce the next PCIe specifications:
PCIe 8.0: 256 GT/s - 2028
PCIe 9.0: 512 GT/s - 2031
PCIe 10.0: 1024 GT/s - 2034
Come on, it's too early! I don't think there are any consumer PCIe 5.0 devices on the market...
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Originally posted by torsionbar28 View PostCool! Like what?
- 10Gbps Ethernet, move it off the 4x/8x slot
- Extra USB3 ports
- Non RAID SATA ports for JBOD
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Originally posted by s_j_newbury View PostThere really isn't any obvious use-case that I can see for such bandwidth, at least outside of HPC or scientific data acquisition, perhaps. It would make more sense to keep to a standard, and reduce system costs, or improve robustness rather than over specify and fragment the market. At least until there is a demonstrable need for something better.
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