Originally posted by brucehoult
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For DMIPS, includes a fair number of P6 (Pentium 3/ Pentium M) representatives. They also have a Pi 3 on there.
Funny to see how poor netburst/P4 actually was per MHz, and you see the huge improvement for core 2.
https://www.eembc.org/coremark/scores.php (search for Pentium)
Yes a more modern compiler might to a little better (especially if it vectorizes some of the loops w/ SSE).
https://bebop.cs.berkeley.edu/resour...ltradeoffs.pdf
A good overview of the P6 architecture. If made today with a comparable front-end, it would be fairly close to an A72/Pi 4. But keep in mind a smaller memory window, longer pipeline, worse branch predictor, and small TLB (16 entry instruction+ 32 entry data, with no L2 TLB supporting it) - Edit - Also keep in mind a better bypass network. All these small details add up to significant improvements.
Edit - The claimed scores for the U74 RISC-V core https://www.sifive.com/cores/u74
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