SiFive's RISC-V HiFive Unmatched Upgraded To Ship With 16GB Of RAM

[microcode]

They also have branch prediction and other fancy stuff. But thats not the point with such a small series silicon by a tiny company.

This SoC has branch prediction though, and it's OoO AFAIK.

[microcode]

I imagine having the performance of a Raspberry Pi 3 or so is the bigger deal killer than a mere 8 GB of RAM. Though I second the call for SO-DIMM slots, which would be nice to have for more ARM systems.

The memory actually seems like the biggest deal, for native building ports of things you can spare time until you have to swap to link your binaries. 16GiB of RAM is enough to link most sane things even with a less efficient linker.

[kgardas]

This SoC has branch prediction though, and it's OoO AFAIK.

No, this is not OoO, this is in-order dual-issue U74. If you like to have OoO you will need to wait for already released SiFive U84 -- but pity, it's not in this board.

[antoinec]

4 cores is very little. All the modern ARM boards have 8 cores.

Completely agree. Do you guys know if there is a risc-v board with more than 64 cores ?

[lyamc]

I don't have much knowledge in the area of CPUs, what sort of benefits/drawbacks come from an OoO cpu vs an in-order cpu?

[microcode]

I don't have much knowledge in the area of CPUs, what sort of benefits/drawbacks come from an OoO cpu vs an in-order cpu?

OoO can improve IPC, and peak performance, but at some performance targets in-order designs typically have better power efficiency. Also, in almost all cases in-order cores have much smaller die footprints.

[Mark Rose]

I don't have much knowledge in the area of CPUs, what sort of benefits/drawbacks come from an OoO cpu vs an in-order cpu?

Out-of-Order means the CPU can re-arrange the instructions being fed to it, as long as the results of the calculation stay the same. If the OoO scheduler can determine it already has the output of a previous calculation in a register, it may pull forward another calculation that can use that value immediately and execute it before another instruction that requires fetching data from cache/memory can be executed. It basically allows the CPU to partially fill bubbles in the execution pipeline. The amount of re-arranging can get complex in modern CPUs, but it does have the downside of using a significant amount of energy in addition to taking up die space.

[jacob]

4 cores is very little. All the modern ARM boards have 8 cores.

And the RISC-V cores are also really weak.

[jacob]

OoO can improve IPC, and peak performance, but at some performance targets in-order designs typically have better power efficiency. Also, in almost all cases in-order cores have much smaller die footprints.

OoO has also suffered from various security issues where the re-ordering of instructions can be exploited in some cases to bypass memory protection, for example. Still, in-order CPUs are now only used in embedded applications or microcontrollers, it is unthinkable to release a general-purpose, high performance processor without OoO execution.

[lyamc]

It makes more sense to release this as an in-order CPU: this is meant to be THE developer platform for RISC-V, and if most of the early development is for mobile and embedded devices then why not make it in-order?