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PCI Express 6.0 Announced For Release In 2021 With 64 GT/s Transfer Rates

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  • #41
    Originally posted by wizard69 View Post
    This has been an interesting read guys but one thing came to mind that might be worth discussion. What are your thoughts on PCI-E 6 being used as a communications channel on multi chip modules? It seems like with the advent of AMD’s chiplet approach and the need to evolve hardware at different rates that this might become a thing. That is use PCI-E 6 to connect GPUs to compute clusters in a single APU like module. Actually I’m thinking it would be an viable interconnect for any high performance subsystem.

    The big advantage is the ability to decouple the evolution of one part of the module from the others. With the density wall soon upon us I’m expecting to see greater use of multi chip modules even at the lower cost end. Having a standard interface, even if it never goes off module seems like a good idea.
    We have similar interconnects within CPU/MDM packages. HyperTransport -> Inifity Fabric for AMD (and others, released 2001 BEFORE PCIe was), and QPI for Intel which was launched in 2008. HT/IF seems, to me, to be the more technically flexible of the two being able to interconnect CPU and other various chips and silicon both on-package and off-package. Things like additional FPGA and other non-CPU ASICs. IF is also set to scale from 30GB/s to 512GB/s, while PCIe 6.0 x16 maxes out at 126.03 GB/s.

    I was thinking HT/IF was mostly just on-board, but it appears they do have slot and chassis interconnect cables specced out. At least for HT. Interesting.