Originally posted by qarium
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The issue with a 7800XT-level IO/GPU die is that the current 7800XT reaches its level of performance because it has 624GB/s of external memory bandwidth which is more than the max 563GB/s that this fictional SOC would have to share between both the GPU and CPU. Current motherboards usually offer four DIMM slots with two 64-bit memory channels. MRDIMMs multiplex the equivalent of two DDR5 DIMMS into one 128-bit memory channel. So assuming motherboards remain at dual channel, that would put a 17,600MT dual channel setup at 563GB/s. That's why I'm treating it as a theoretical max for now. I think that's fair considering we're comparing the the external memory bandwidth requirements of current generation AMD CPUs and GPUs and the bandwidth that can provided by the third generations of an unreleased DIMM standard.
This fictional Navi 32 IO die wouldn't be a regular Navi 32 GCD re-used, it would be Navi 32 with the addition of the four SerDes interfaces, 2 IFOP PHYs , the security processor, USB controllers and PHYs that are on the IO die which would make the Navi 32 I/O die larger than a Navi 32.
The next GPU that slots into the 7800XT's slot, whether that be a 8800XT or 9800XT, will require even more bandwidth.
Originally posted by qarium
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The advantages of chiplets is that they vastly reduce costs by improving yields, requiring fewer large chips to be created, and allow dies to be allocated to different designs but they have their downsides, too. Chiplets tend to put components physically farther away from each other than they would be if the blocks were monolithic. Bring traffic off-die which uses more power, increases latency, makes it harder to connect them at high bandwidths, and the interfaces needed to connect them often make the individual chiplets larger than they would be if they were blocks in a monolithic chip. That's why AMD has always put eight cores on a CCD even when CCDs contained two CCXs.
Currently, chiplets aren't really more advanced than what was done in Multi-chip Modules and those have been around for years. The Wii U literally had a 3-core CPU chip connected to a GPU/IO die with memory controllers on one package back in 2012. There are ideas to get around the disadvantages of chiplets though like bridging chiplets, active interposers, etc. They're not here yet though, so chiplet designs need to figure out what makes the most sense to divide and what should be kept together. Those decisions are often going to be determined based on what you want your whole product to look like.
In AMD's case, they already have 8 core SOCs but their iGPUs fall way short of a 7800XT. If they could scale up their GPU compute with chiplets then they could just use GPU chiplets to expand their small SOCs into larger SOCs. The Ryzen Pro 7940HS has eight Zen 4 cores and 12 CUs. Lets say that it was given 16MB of Infinity Cache. Then it could be paired with a chiplet that includes 48 CUs, 48MB Infinity Cache, and a few more 64-bit memory controllers then it you get an SOC with eight Zen 4 cores and an iGPU with 60 CUs, a 256-bit bus, and 64MB of Infinity Cache just like the 7800XT.
That same 48 CU chiplet could be doubled up and paired with a front-end chiplet to make something between a 7600 and 7700XT. Add another one of those chiplets and you now have a 7900XTX. Imperfect chiplets could have CU, memory, controllers and Infinity Cache banks disabled to make other SKUs.
That way you get your monolithic mobile SOCs, your big SOCs, and your entire GPU line out of 3 chiplets and none of them are as large as a Navi 32.
That can't happen though because they can't scale their GPU compute with chiplets.
Originally posted by qarium
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Originally posted by qarium
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