Libre RISC-V Accelerator Secures 300k EUR In Grants, Still Undecided About The ISA

[programmerjake]

I can definitely see how, for a project called "Libre RISC-V", the ISA is a point of debate.
</s>

Especially when they've received a bunch of grants, under that name.

We're planning on having the GPU be able to run RISC-V code even if we decide to use OpenPower, it would then support at least RV64GC user mode so programs that don't use our graphics extensions would still run at full speed. This would be implemented similarly to how x86-64 Linux can still run x86-32 programs. See the thread about that: http://lists.libre-riscv.org/piperma...er/003104.html

[OneTimeShot]

Wow - from what I've seen of the Libre RISC-V GPU project (which isn't much - they haven't even picked POWER or RISC-V) this is going to be money down the drain.

[microcode]

I can definitely see how, for a project called "Libre RISC-V", the ISA is a point of debate.
</s>

Especially when they've received a bunch of grants, under that name.

[starshipeleven]

According to lkcl in a previous phoronix thread, many of those require proprietary compilers, and the remaining ones were made in some hard to work with custom language. This project would be usable entirely with FOSS.

For those following from home, the high-complexity modern electronic integrated circuits aren't designed graphically like you would design a printed circuit board with traces and stuff.
You literally have billions of logic gates all over the place, it's not practical in the slightest.

You "write" the integrated circuit design in "electronics design code" (Hardware Description Language, HDL) which is then read and "compiled" by a compiler software into a phyisical design that the fab can manufacture.
Examples of such languages would be Verilog and VHDL.

[curaga]

There already exist a bunch of opensource RISC-V implementations: https://github.com/riscv/riscv-cores-list How about taking one of those and add the Vector extension to it?

According to lkcl in a previous phoronix thread, many of those require proprietary compilers, and the remaining ones were made in some hard to work with custom language. This project would be usable entirely with FOSS.

[aht0]

curaga it's impossible to implement.

[pkese]

@pkese: The point of this SoC is to create an entirely libre processor.

There already exist a bunch of opensource RISC-V implementations: https://github.com/riscv/riscv-cores-list
How about taking one of those and add the Vector extension to it?
The Pulpino ARA implementation reached 34 GFLOPS with dual precision (67 DP-GFLOPS/W) and had reached silicon implementation.

I'm trying to understand how is this different (i.e. what's the innovative contribution, besides the 'not invented here' syndrome)...

[WolfpackN64]

@pkese: The point of this SoC is to create an entirely libre processor. Source code for everything, verifiable, customizable - you can be sure there are no backdoors, that the chip is doing what you want it to. You can hack on it. The initial performance targets are for a cheap node (180nm costs a tiny part of modern nodes) and low power budget - it's not going to be a performance killer, it's the first implementation. However it will fill the goal of a libre processor, and improvements to both design and smaller nodes will come.

This. If you're starting with this kind of proof of concept Vulkan accelerator, better to try something you can realistically produce as a first generation product with realistic performance expectations and then work from there.

[curaga]

@pkese: The point of this SoC is to create an entirely libre processor. Source code for everything, verifiable, customizable - you can be sure there are no backdoors, that the chip is doing what you want it to. You can hack on it. The initial performance targets are for a cheap node (180nm costs a tiny part of modern nodes) and low power budget - it's not going to be a performance killer, it's the first implementation. However it will fill the goal of a libre processor, and improvements to both design and smaller nodes will come.

[pkese]

What's the point of building a 5-6 GFLOPS CPU/GPU (considering that a $35 Raspberry PI GPU has 24 GFLOPS).

It seems that the technological agenda here is way behind the political one (including bashing of RISC-V ISA).