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Raspberry Pi Pico 2 W Launches For $7

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  • Raspberry Pi Pico 2 W Launches For $7

    Phoronix: Raspberry Pi Pico 2 W Launches For $7

    Complementing the Raspberry Pi Pico 2 that launched this summer, the Raspberry Pi Pico 2 W was announced today for $7 as the wireless-enabled variant of this small microcontroller board...

    Phoronix, Linux Hardware Reviews, Linux hardware benchmarks, Linux server benchmarks, Linux benchmarking, Desktop Linux, Linux performance, Open Source graphics, Linux How To, Ubuntu benchmarks, Ubuntu hardware, Phoronix Test Suite

  • #2
    How does this compare to the esp32 family in features and power consumption?

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    • #3
      Originally posted by geerge View Post
      How does this compare to the esp32 family in features and power consumption?
      Don't know either, but here's just a glance at the specs:

      ESP32:
      • CPU:
        • 1 core at 240 MHz
        • 2 cores at 240 MHz
      • RAM: 520 KB SRAM + 16 KB SRAM in RTC
      • ROM: 448 KB
      RPI Pico 2:
      • CPU: Dual Arm Cortex-M33 @ 150MHz
      • RAM: 520 KB on-chip SRAM
      • ROM: 4 MB on-board QSPI flash
      Take from that what you will.

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      • #4
        You seem to have missed that this new microcontroller also has 2 RISC-V cores on board and can be booted in “RISC-V mode” which is really cool.

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        • #5
          Doesn't this chip still have terrible errata.

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          • #6
            Originally posted by Developer12 View Post
            Doesn't this chip still have terrible errata.
            Every Ax stepping is going to have errata. That's just the nature of silicon. The only difference is that Raspberry Pi tells you about it instead of quietly working around it in the SDK.

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            • #7
              Originally posted by scottishduck View Post
              You seem to have missed that this new microcontroller also has 2 RISC-V cores on board and can be booted in “RISC-V mode” which is really cool.
              esp32 has half a dozen variants many of which are risc-v. C3 looks to be base risc-v, C6 is RV32IMAC, the "announced" P4 has RV32IMAFC_Zicsr_Zifencei. The rp2350 in the pico says this in the datasheet:
              3.8.1.2. Architecture Strings
              -march strings completely specify the set of available RISC-V instructions, so that a compiler can generate correct and
              optimal code for your device. Use the following in descending order of preference:
              1. Use rv32ima_zicsr_zifencei_zba_zbb_zbs_zbkb_zca_zcb_zc mp for compilers which support the Zcb and Zcmp extensions,
              such as GCC 14.
              2. Use rv32ima_zicsr_zifencei_zba_zbb_zbs_zbkb_zca_zcb for GCC 14 packaged with an older assembler which does not
              support Zcmp.
              3. Use rv32imac_zicsr_zifencei_zba_zbb_zbs_zbkb for older compilers, such as GCC 13 and below.​
              So the P4 has an FPU, the risc-v in the pico instead has what looks to be bit manipulation extensions. Pico is 3 stage in-order pipeline, no idea what the various esp32 models are.

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              • #8
                Still No USB-C?

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                • #9
                  Originally posted by Lycanthropist View Post
                  Still No USB-C?
                  For the original Pico, you could buy a YD-RP2040 off Aliexpress. They cost less when including shipping, use the same chip, and the only caveat I've found is that, if you want to build a ps2x2pico, you'll need to bridge two legs of a Y-diode where the original design didn't separate things to allow current to flow from the PS/2 port to the USB keyboard and mouse if you're not using a powered USB hub. (I contributed a photo showing what to bridge for that one.)
                  Last edited by ssokolow; 25 November 2024, 12:29 PM.

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                  • #10
                    Originally posted by scottishduck View Post
                    You seem to have missed that this new microcontroller also has 2 RISC-V cores on board and can be booted in “RISC-V mode” which is really cool.
                    It's also possible to have one core running arm + one core running riscv.

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