AMD CDX Being Prepared For Linux As The Bus Between Future APUs & FPGAs

[phoronix]

Phoronix: AMD CDX Being Prepared For Linux As The Bus Between Future APUs & FPGAs

After quietly posting a "request for comments" patch series a few months back to no fanfare, AMD today published their post-RFC patch series today for introducing the AMD CDX bus to the Linux kernel. AMD CDX is ultimately for the interface/bus between the APU and FPGA(s) with future hardware...

https://www.phoronix.com/news/AMD-CDX-APUs-FPGAs-Linux

[Jumbotron]

Interesting. Along with juicy rumors of AMD's upcoming "Strix" APU being a Zen 5 part with RDNA 3+ iGPU this could make APUs finally something we had all hoped for 10 years ago with the Fusion era APUs or at least was hyped by AMD during the pre-Su days. I also find it interesting the inclusion of CDX with the Arm MMU. Obviously Xilinx FPGAs are ARM based themselves but now that AMD's GPUs are showing up in Samsung's Exynos SoCs and giving Qualcomm's latest Snapdragon SoC a run for it's money particularly in Raytracing the addition of both an AMD GPU and FPGA in an ARM SoC is rather intriguing.

[brucethemoose]

Could this be an enterprise APU only thing?

I can see this as an updateable media decode/encode block, but I am struggling to think of other niches a small fpga could efficiently fill in laptops...

Cryptography acceleration?
Maybe network stuff?

Those seem highly dependent on library/app support, while its more reasonable to expect decode/encode to "just work" since its going through some AMD driver anyway.

[DarkCloud]

Interesting. Along with juicy rumors of AMD's upcoming "Strix" APU being a Zen 5 part with RDNA 3+ iGPU this could make APUs finally something we had all hoped for 10 years ago with the Fusion era APUs or at least was hyped by AMD during the pre-Su days. I also find it interesting the inclusion of CDX with the Arm MMU. Obviously Xilinx FPGAs are ARM based themselves but now that AMD's GPUs are showing up in Samsung's Exynos SoCs and giving Qualcomm's latest Snapdragon SoC a run for it's money particularly in Raytracing the addition of both an AMD GPU and FPGA in an ARM SoC is rather intriguing.

I believe Qualcomm's gpu was purchased from AMD sometime ago. so AMD seems to be competing with itself Quite amazing how AMD keeps innovatiing.

[Jumbotron]

Correct. Qualcomm's GPU is called Adreno and is actually an anagram of Radeon. ATI which was bought by AMD had developed a mobile chipset called Imageon. Sometime after the purchase AMD sold off the entire Imageon division and IP to Qualcomm. There is still a crap ton of code labeled ATI and AMD in the Adreno code base. And yes it is odd to see Qualcomm with AMD tech in their GPU compete with Samsung's Exynos with an actual AMD GPU.

[vein]

Could this be an enterprise APU only thing?

I can see this as an updateable media decode/encode block, but I am struggling to think of other niches a small fpga could efficiently fill in laptops...

Cryptography acceleration?
Maybe network stuff?

Those seem highly dependent on library/app support, while its more reasonable to expect decode/encode to "just work" since its going through some AMD driver anyway.

Hmm...isn't this support for the xdna AI-chip thingy from xilinx that is already announced in the upcoming 7040 Phoenix Ridge APU series?

(I really want a nice thinkpad with one of these )

[osw89]

Sorry to disappoint everyone but this has nothing do with the APUs(processor + integrated graphics) you are thinking about. In higher end Xilinx SoCs there are both general purpose Cortex-A53 cores and fewer (usually two) Cortex-R5F cores that are intended for real-time operations. They call the general purpose A53 cores Application Processing Unit (APU) and the R5Fs Real-Time Processing Unit (RPU), that's what they mean with APU. Even though it sounds very nice, especially to me, they really don't have a reason to waste precious die area to add programmable logic to consumer parts. The two most important things the average consumer might need acceleration for are graphics and video decoding, consumer parts already have dedicated logic for those.

According to one of the commits this bus "caters to the requirement for dynamically discovered FPGA devices" so it should make it possible to reprogram the FPGA part while the ARM side is running linux and have things work.

[brucethemoose]

osw89 Oof, that makes sense.

But on the other hand, the integration of some Xilinx IP was already sorta announced? https://twitter.com/david_schor/stat...29109738881024

Hmm...isn't this support for the xdna AI-chip thingy from xilinx that is already announced in the upcoming 7040 Phoenix Ridge APU series?

(I really want a nice thinkpad with one of these )

Pure FPGAs arent a great fit for AI acceleration. I suspect the "Xilinx AI Engine" in Phoenix Ridge is probably more ASIC than FPGA, assuming its even programmable at all, and that osw89's assertion that this has nothing to do with the graphics heavy APUs is correct.

[osw89]

osw89 Oof, that makes sense.

But on the other hand, the integration of some Xilinx IP was already sorta announced?
.

That probably is fixed-function silicon, ASICs are better in terms of performance and power so I doubt they would put programmable stuff on a ryzen chip. It's mostly something similar to the neural engine in Apple's chips. And while talking of IPs(ready to use logic blocks you can use in hardware design like peripherals), xilinx has a lot of them and they have linux support. The cores in their FPGA SoCs use the AXI bus currently. You can design your own logic and/or use their IPs which can be connected to the CPUs using AXI. Like a processor with customizable peripherals if you will. https://xilinx-wiki.atlassian.net/wi.../Linux+Drivers

osw89
I suspect the "Xilinx AI Engine" in Phoenix Ridge is probably more ASIC than FPGA, assuming its even programmable at all, and that osw89's assertion that this has nothing to do with the graphics heavy APUs is correct.

I would say we're both right . The only reason to use an FPGA in a mass produced product would be low volume since the chip being programmable doesn't matter to the consumer that much. Also here's an excerpt from one of the commits "Devices in FPGA can be added/modified dynamically on run-time. These devices are exposed on system bus to embedded CPUs. Xilinx CDX bus, caters to the requirement for dynamically discovered FPGA devices." https://lwn.net/Articles/904975/. You can program the CPUs and the FPGA portion separately so this new bus was probably created to make the reprogramming of only the FPGA while running Linux easier.

[brucethemoose]

That probably is fixed-function silicon, ASICs are better in terms of performance and power so I doubt they would put programmable stuff on a ryzen chip.

On this subject, I was a bit confused and thought Phoenix was the 8000 series. Its actually the 7040 series that AMD already announced this month:

csm_amd_phoenix_hs_6_334a253c1d.jpg

That maybe kinda looks like a programmable layer hooking fixed function blocks together? I hope AMD elaborates on this more.