Raspberry Pi Supply Chain Issues Beginning To Ease Up

[coder111]

Think the raspberry platform with SATA interface would be great for a NAS, network attached storage, system.

Too bad we need to go running around for the SATA add-in boards.

I wish my NAS would have ECC RAM. I don't think RPI4 has ECC RAM, does it?

[caligula]

LOL, no. The Pi prioritizes low-cost above all else. That rules out 32 GB and probably even 16 GB, for the next iteration. Furthermore, you don't really need more than 8 GB, so long as it has just 4 cores.

Maybe not as a headless server, but many use RPi as a desktop system. Phones already ship with 12-18 GB of RAM. Sub $1000 laptops come with 16GB.

Pfft! What planet are you on? Lately, 10 Gbps Ethernet MACs cost more than the Pi's Broadcom SoC! Not only that, but it's entirely unnecessary for at least 99% of the Pi's users!

Look at this board: https://www.servethehome.com/the-gow...-intel-nvidia/
This is only barely more expensive than RPi 4, yet contains both triple 2,5 Gb and dual 10 Gb ports

You can't even buy PCIe 5.0 M.2 drives, yet! Even if you could, a Pi-class SoC could never push them past probably even PCIe 3.0 speeds!

Well, there are already plans, I'd expect those to ship in 12 months: https://www.youtube.com/watch?v=4PkJQw1mgB0

[mangeek]

For reference, Apple uses LPDDR memory in its M-series. The baseline M1 and M2 SoCs have a data width of 128 bits. The M1 Pro/Max use 256 bits. The Ultra is 2x Max, and therefore 512 bits.

But, that's Apple. I think the main benefit they get by putting the DRAM in-package is size. Power-savings and increased-width are secondary benefits. Perhaps there's some cost-savings, especially at such width?

I don't know how much cost it adds to build a MCM, but I'm going to venture a guess that it would probably be a wash at 64 bits. Because it's cost-optimize, I'd guess the Pi would rather go with a higher-clocked LPDDR than increase width to 64-bit. Especially to the extent the SoC is developed in tandem, since going to 64-bit would actually involve adding an entire extra channel.

Again, I don't know the details of such things, but I thought Apple moved the memory close to the CPU was so they could have a really big fat pipe between the GPU, CPU, and RAM; that lets them squeeze more than you'd expect from the processing components. In a Raspberry Pi, I'd imagine that bringing the memory close could let them widen the pipe and keep the CPU/GPU fed without having to add traces to the board (it would reduce them instead). It's less flexible, but I think that's where the 'guaranteed volume' of the Raspberry Pi sales could save the day. I think the RPI folks could be less risk-averse in the next iteration of their product, especially if they have a higher margin flagship leading the way instead of building up to it from their low-cost 2GB models.

[coder]

I was wondering if getting the RAM closer to the CPU opened any options, like a wider data path. I have no idea if that would even be helpful, but I reading that the real-world memory bandwidth of the Pi 4 is far short of what the components are capable of, probably mostly due to the VC6 being first in line to the RAM?

For reference, Apple uses LPDDR memory in its M-series. The baseline M1 and M2 SoCs have a data width of 128 bits. The M1 Pro/Max use 256 bits. The Ultra is 2x Max, and therefore 512 bits.

But, that's Apple. I think the main benefit they get by putting the DRAM in-package is size. Power-savings and increased-width are secondary benefits. Perhaps there's some cost-savings, especially at such width?

I don't know how much cost it adds to build a MCM, but I'm going to venture a guess that it would probably be a wash at 64 bits. Because it's cost-optimize, I'd guess the Pi would rather go with a higher-clocked LPDDR than increase width to 64-bit. Especially to the extent the SoC is developed in tandem, since going to 64-bit would actually involve adding an entire extra channel.

[mangeek]

Porting to a smaller node would offer some more frequency headroom, but not enough to be worth doing it just for that. More importantly, die costs would probably still go up, for smaller nodes. Their policy is to use the node with the lowest per-transistor cost.

I wasn't even thinking about performance or thermals, I was thinking about getting the sheer volume of chips they need from the factory. The 28nm manufacturing equipment is in very high demand these days. I don't know the exact economics, but I gather you can get almost 3x as many chips from a 16nm wafer vs. a 28nm one... so even if the cost of the wafer doubles, it seems like it might be a net win.

The cost of making a MCM would probably outweigh the benefits. The Pi uses just a 32-bit datapath for its LPDDR4, which isn't costly or difficult to route.

This sort of thing is way above my pay grade, but I was wondering if getting the RAM closer to the CPU opened any options, like a wider data path. I have no idea if that would even be helpful, but I reading that the real-world memory bandwidth of the Pi 4 is far short of what the components are capable of, probably mostly due to the VC6 being first in line to the RAM?

[rogerx]

Think the raspberry platform with SATA interface would be great for a NAS, network attached storage, system.

Too bad we need to go running around for the SATA add-in boards.

[jaxa]

I'm not really sure how 12 GB happens... I think the Pi's DRAM is single-die? Are there 96 Gbit LPDDR4 dies out there?

Single package 12 GB LPDDR4X exists. Also 12 GB LPDDR5, and the ultimate is 18 GB. Maybe 20-24 GB LPDDR5X in the next couple of years.

https://en.wikipedia.org/wiki/LPDDR#LPDDR4X

I think the memory manufacturers can stack at least 8-12 dies in a package, maybe 16-32 in the near future.

[coder]

Eben Upton whispered to me in a dream and told me that Pi5 is a quad-core Cortex-A75 with no NVMe. It will be much worse than the RK3588, but $100 cheaper and a reliable uplift over the Pi4.

I agree, except for the cost differential. Maybe compared with boards using the standard RK3588, but there's a cost-reduced RK3588S, which mainly seems to cut down on things like PCIe, without seeming to compromise on CPU performance. That's what the $83 Orange Pi 5 uses.

Maybe 12-16 GB. A nice and aggressive move would be if RPi replaces 8 GB with 12 or 16.

I'm not really sure how 12 GB happens... I think the Pi's DRAM is single-die? Are there 96 Gbit LPDDR4 dies out there?

[coder]

I recall the RPI using an older process node than the typical Cortex-A72's 16nm. Would it have been possible for RPI to work with Broadcom to do a 'refresh' of the BCM2711 that was on a less congested manufacturing node, or is that a huge lift?

It uses 28 nm. And it's the first to do so, as all of its predecessors used 40 nm. Porting to a smaller node would offer some more frequency headroom, but not enough to be worth doing it just for that. More importantly, die costs would probably still go up, for smaller nodes. Their policy is to use the node with the lowest per-transistor cost.

If they shrank the CPU core, could they put 8GB RAM in the package? Seems like that would cut down on parts...

The cost of making a MCM would probably outweigh the benefits. The Pi uses just a 32-bit datapath for its LPDDR4, which isn't costly or difficult to route.

[coder]

I'd expect the next iteration to come with 16 to 32 gigs of RAM.

LOL, no. The Pi prioritizes low-cost above all else. That rules out 32 GB and probably even 16 GB, for the next iteration. Furthermore, you don't really need more than 8 GB, so long as it has just 4 cores.

RPi just needs to strike first.

LOL, no. The Pi was never about being first or fastest. It needs to be easy, cheap, stable, and adequate. Pretty much in that order.

It needs faster IO.

I doubt it'll happen. Not if it adds any cost. However, I think there's a fairly recent standard for doing NVMe over SD, which is probably the best hope. If that can be implemented with minimal hardware cost and without breaking compatibility with standard microSD cards, I could see it happening.

Again I'd expect 10 Gbps LAN.

Pfft! What planet are you on? Lately, 10 Gbps Ethernet MACs cost more than the Pi's Broadcom SoC! Not only that, but it's entirely unnecessary for at least 99% of the Pi's users!

Maybe the Pi 6 might stretch to 2.5 Gbps, but that's as far & as soon as I see it happening.

People need at least 10 Gbps LAN + WAN ports for routing internet traffics. Preferably a CM5 carrier board with a 4 or 8-port 10 Gbps programmable switch.

No kind of Pi will ever accommodate such a thing. What you are describing is more like what they sell here:

https://www.solid-run.com/arm-server...ing-platforms/

Or maybe you can use one of these for something like what you have in mind:

• https://www.solid-run.com/embedded-n...-computer-sbc/
• https://www.solid-run.com/embedded-n...earfog-cn9130/

A PCIe 5.0 4x slot.

Wow. Just wow.

That's already a couple times as fast as the Pi 4's entire memory bandwidth. It would blow up PCB size, cost, & complexity, increase power consumption, and for what? You can't even buy PCIe 5.0 M.2 drives, yet! Even if you could, a Pi-class SoC could never push them past probably even PCIe 3.0 speeds!