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Mesa Drops Support For AMD Zen L3 Thread Pinning, Will Develop New Approach

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  • Mesa Drops Support For AMD Zen L3 Thread Pinning, Will Develop New Approach

    Phoronix: Mesa Drops Support For AMD Zen L3 Thread Pinning, Will Develop New Approach

    It was just a few months back that the Mesa/RadeonSI open-source AMD Linux driver stack received Zen tuning for that CPU microarchitecture's characteristics. But now AMD's Marek Olšák is going back to the drawing board to work on a new approach for Zen tuning...

    http://www.phoronix.com/scan.php?pag...L3-Thread-Pins

  • #2
    honestly i would have prefered the driconf approach until the new one was submitted, anyway it doesnt affect me personally because ryzen APUs have only one CCX

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    • #3
      Am I being naive in thinking that Linux kernel know about CPU layout and attempt to manage this? it seems that this is more of a scheduling problem...

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      • #4
        Originally posted by boxie View Post
        Am I being naive in thinking that Linux kernel know about CPU layout and attempt to manage this? it seems that this is more of a scheduling problem...
        No, you're absolutely correct that it should be handled like that in the kernel. But creating a new kernel api to handle that is a lot of work and will undoubtedly trigger a bunch of pushback, so it makes sense to try and get something working inside Mesa if they can. (It has to be the app telling the kernel which threads to schedule together, because the kernel won't know on it's own).

        Anyway, Marek's already posted 2 new patches to try and do this same thing better. Hopefully people test them out and they work.

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        • #5
          Originally posted by smitty3268 View Post

          No, you're absolutely correct that it should be handled like that in the kernel. But creating a new kernel api to handle that is a lot of work and will undoubtedly trigger a bunch of pushback, so it makes sense to try and get something working inside Mesa if they can. (It has to be the app telling the kernel which threads to schedule together, because the kernel won't know on it's own).

          Anyway, Marek's already posted 2 new patches to try and do this same thing better. Hopefully people test them out and they work.
          Thanks for the info - I am sure the Kernel path would be more difficult, but it would technically be the better solution that would benefit more than just gaming. and as AMD go further down the chiplet path - probably more and more important to consider

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          • #6
            Originally posted by boxie View Post
            Am I being naive in thinking that Linux kernel know about CPU layout and attempt to manage this? it seems that this is more of a scheduling problem...
            Technically you are correct - this is a scheduling problem. The challenge is that AFAIK we do not have way to pass sufficiently rich information about scheduling requirements/constraints for the scheduler to make sufficiently good decisions.

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            • #7
              Originally posted by bridgman View Post

              Technically you are correct - this is a scheduling problem. The challenge is that AFAIK we do not have way to pass sufficiently rich information about scheduling requirements/constraints for the scheduler to make sufficiently good decisions.
              Interesting, is that because this info passing does not exist in the kernel?

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              • #8
                Hopefully with Zen 2 and its much improved inter-core-latency, this problem will go away soon.
                Last edited by ms178; 13 November 2018, 03:55 AM.

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                • #9
                  Not sure if this is going to be an issue with Zen 2 also, but in case it's not, is it even worth putting work into this? Yes, I'm saying that as a Ryzen 1700X owner, but if the issue is exclusive to us early adopters that has the first generation of Zen CPU's then the userbase affected isn't that huge.

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                  • #10
                    Originally posted by Brisse View Post
                    Not sure if this is going to be an issue with Zen 2 also, but in case it's not, is it even worth putting work into this? Yes, I'm saying that as a Ryzen 1700X owner, but if the issue is exclusive to us early adopters that has the first generation of Zen CPU's then the userbase affected isn't that huge.
                    They might want to live up to their "Fine Wine" anology. There were some promising results mentioned on the mailing list, so in the end, the effort might be worth a try. And it seems that Marek did come up with an answer rather quickly. It also makes business and marketing sense for AMD to invest some effort into making sure that their GPU driver stack works well on their own CPU products. Nvidia might not have that incentive.

                    If it happened even sooner in the Zen 1 life cycle it could have helped them to drive even more GPU and CPU sales as CCX latency and scheduling interaction with the driver might be one source of Ryzen's relative weakness in gaming performance.

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