Originally posted by chithanh
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The google foo jury is out as far as a simple yes/no is concerned. I thought I found an answer but it was DDR4 command/address parity checking (bus parity) not ECC.
Aha... so the data bus is 72 bits - 64 for data, 8 for ECC. In non-ECC DIMMs the extra 8 bits are used for address/command parity. These features are mutually exclusive. Either you have non-ECC DIMMs with command/address parity, or you have ECC DIMMs with error correcting codes. The mode is controlled via a single trace - PARITY and reporting is via the ERROR_N trace. The modality is controlled by the memory controller. So yes, the Ryzen cores with integrated memory controller can switch between ECC and non-ECC in software so long as the motherboard extends the PARITY trace to the sockets. Otherwise the socket will be locked in one mode or the other.
So jury is still out because we don't know whether that trace exists on the Octopus mobo.
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