Tilera TILE64 Back-End For LLVM Published
An LLVM back-end was released by a user for TILE64, the multi-core Tilera processor packing 64 tiles, a.k.a. a processor, cache, and non-blocking router. TILE64 builds upon a MIPS-derived VLIW instruction set with the processor itself targeting networking and digital video environments with high performance needs.
GCC has been supporting various Tilera CPUs, Linux has supported TILE64 since the Linux 2.6.36 kernel, and now support is being enabled within LLVM.
The LLVM back-end for TILE64 has yet to be merged but currently is living separately from the LLVM code-base. With the LLVM 3.1 back-end, it's a "minimalist functioning implementation." The developer, David Juhasz, is now working on utilizing LLVM's VLIW packetizer and making other improvements.
This work is being done out of the Eötvös Loránd University in Hungary. The LLVM/Clang TILE64 back-ends for LLVM 3.1 and an LLVM 3.2 SVN snapshot can be found here. Additional information is available from the LLVM development announcement.
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