The RISC-V GCC port has been a work in progress for a long time and was held up by university lawyers while that was all cleared up, the code went through a few rounds of code revisions, and the steering committee approved landing RISC-V support even as the codebase has moved onto only bug/regression fixes. Today all of that code finally was merged into the GCC7 code-base.
There was the new port, libgcc changes and several other patches landing this code into the GNU Compiler Collection 7.
GCC 7 is expected for release in the next month or two. RISC-V is a promising, royalty-free processor ISA and the compiler port for it supports version 2.0 of the RV32I and RV64I ISAs. Learn more about this open-source processor ISA at RISCV.org.