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Here's The AMD Llano Fusion Mesa/Gallium3D Code

AMD

Published on 31 May 2011 07:17 PM EDT
Written by Michael Larabel in AMD
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It wasn't only the Llano DRM/KMS kernel support that was pushed to the community by AMD today for their next-generation Fusion hardware, but the Mesa/Gallium3D support has landed in place too. This code was pushed into Mesa master (meaning it will hit the Mesa 7.11 release) and there was also the X.Org bits landing in the xf86-video-ati DDX.

With a supportive Radeon DRM driver, landing the user-space Mesa bits for the 32nm Llano is rather trivial. Bring up the Llano support -- via the SUMO and SUMO2 family names -- only meant 65 lines of code had to be added to the existing R600g Gallium3D driver. The code changes were largely just adding in the SUMO/SUMO2 and PCI ID recognition for the new hardware and reporting its driver capabilities.

0x9640, 0x9641, 0x9647, 0x9648, 0x964a, 0x964e, 0x964f are the seven PCI IDs for the initially supported Llano/SUMO chips and then 0x9642, 0x9643, 0x9644, and 0x9645 are the four from the SUMO2 family. View the commit here.

With landing Llano support being so trivial, support was also added to the "R600c" classic Mesa driver too. That too took less than 100 lines of code changes, per this commit.

In the xf86-video-ati DDX land, the Llano support is now living in master too. It took two commits (one and two). With only the KMS code paths being worked on for future hardware, these changes too weren't much without having to worry about user-space mode-setting. This code simply enables EXA and X-Video acceleration.

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