Intel Gets AVX-512 Support Going In GCC
Written by Michael Larabel in Compiler on 10 February 2014 at 09:06 AM EST. 5 Comments
The forthcoming release of the GCC 4.9 compiler will feature support for Advanced Vector Extensions 512 (AVX-512) although this instruction set extension won't be appearing on Intel CPUs for a while.

Advanced Vector Extensions 512 succeeds AVX2 from Haswell but isn't expected to make its debut in Intel processors until likely the launch of the "Skylake" processors in late 2015 or 2016. Being realized likely before the Skylake launch but out of reach to most Phoronix readers will be Intel's "Knights Landing" Xeon Phi that also supports AVX-512. The Knights Landing hardware is where AVX-512 capabilities should be fully realized.

AVX-512 has 32 vector registers that are 512-bit wide and supports 512-bit operations on packed floating point and integer data. AVX-512 also has a new EVEX coding scheme over AVX1/AVX2. The AVX-512 support that's been added to GCC this month is the inline assembly support, support for AVX-512's new registers and extending the existing registers, the intrinsics set, and basic auto-vectorization support. GCC adds a "-mavx512f" compiler switch for AVX_512 Foundation support, "-mavx512pf" for the AVX-512 pre-fetch instructions, "-mavx512er" for the AVX-512 exponential and reciprocal instructions, and "-mavx512cd" for AVX-512 conflict detection instructions.

More details on the AVX-512 support in GCC 4.9 can be found via this patch and the AVX GCC commit activity.
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Michael Larabel is the principal author of Phoronix.com and founded the site in 2004 with a focus on enriching the Linux hardware experience. Michael has written more than 10,000 articles covering the state of Linux hardware support, Linux performance, graphics drivers, and other topics. Michael is also the lead developer of the Phoronix Test Suite, Phoromatic, and OpenBenchmarking.org automated benchmarking software. He can be followed via Twitter or contacted via MichaelLarabel.com.

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