LLVM Working On Intel AVX-512 Support
Written by Michael Larabel in Intel on 5 August 2013 at 03:42 PM EDT. 11 Comments
Intel developers working on the LLVM compiler infrastructure have been working on AVX-512 instruction set support in recent days. Intel AVX-512 instructions support 512-bit SIMD instructions with providing twice the number of data elements handled by AVX/AVX2 with a single instruction and four times that of SSE instructions.

Intel AVX-512 is designed for demanding computational tasks with having 512-bit wide 32 vector registers, eight dedicated mask registers, high speed math instructions, and other new capabilities over existing Advanced Vector Extensions.

On the hardware side, Intel will be introducing AVX-512 to their Xeon Phi co-processors with "Knights Landing" (the 14nm update to Knights Corner) and later will come to traditional Xeon CPUs.

For more details on Intel AVX-512 instructions, read the documentation at software.intel.com. The recent AVX-512 operations support in LLVM can be found from the GitHub mirror commit list.

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