Tilera Publishes TILE-Gx CPU Back-End To LLVM

After already having integrated TILE-Gx support into GCC 4.7, Tilera is now calling for the mainlining of its TILE-Gx back-end into LLVM. The LLVM Tile-Gx back-end is needed for the company's forthcoming many-core processor.

TILE-Gx is a VLIW architecture with load-store architecture ISAs. The CPU uses 64-bit registers, address space, and instructions. In mid-February, Tilera announced they would be releasing a 72-core Tile-Gx CPU. The 64-bit processor also features 32KB of L1 cache per core, 256KB L2 cache per core, up to 26MB of L3 cache, dual or quad ECC 72-bit DDR3 memory controllers, and a built-in crypto accelerator.

Tilera's TILE-Gx product page says the architecture is optimized for "networking, video, and cloud applications. It delivers the highest performance per watt per square inch with complete 'system-on-a-chip' features."

Tilera TILE-Gx support was first found in the GNU Compiler Collection with version 4.7 last year. Last year was when Tilera pushed out a TILE64 back-end for LLVM. If the TILE-Gx back-end is merged into LLVM mainline (there's nothing right now suggesting the back-end will be turned down), it will likely be found in LLVM 3.3 when released in the coming months.