GCC Prepares Compiler Support For Intel Broadwell
Written by Michael Larabel in Compiler on 26 February 2013 at 07:43 PM EST. Add A Comment
While Intel Haswell processors won't even be released to the public until later this year, compiler developers have already been working on supporting the new instruction set extensions of Haswell for more than one year. GCC developers already have early Intel Broadwell support ready for GCC 4.8.

One of the many features that will be part of the GNU Compiler Collection 4.8 release when it happens in the next month or two is initial Intel Broadwell support. Haswell support was already found in GCC 4.7 and improvements in 4.8, so in months prior these free software developers have already been hitting a large chunk of the Broadwell additions. Broadwell is the 14nm die shrink of Haswell due out likely in mid-2014. Broadwell is notable in that it moves to a Multi-Chip Package design, but as it concerns compiler developers, there are new instructions to support.

The hardware instructions that are now supported in GCC 4.8 for Intel Broadwell include:

RDSEED - GCC already supports RDRAND (a.k.a. "Bull Mountain") of Ivy Bridge / Haswell while Broadwell brings RDSEED. RDSEED is for generating 16/32/64-bit random numbers in accordance with the NIST SP 800-90B and 800-90C standards.
ADCX/ADOX - ADCX and ADOX are new arbitrary precision integer operations with the difference between the two instructions being how the integers are added.
PREFETCHW - Intel's PREFETCHW instruction is similar to AMD's pre-fetch handling.

These new ISA extensions are exposed in GCC via the -madx, -mprfchw, -mrdseed compiler switches.

While not part of the Broadwell enablement, GCC 4.8 for Intel also supports Intel RTM and HLE intrinsics. HLE is the Hardware Lock Elisions and RTM is for Restricted Transactional Memory. These new supported Intel intrinsics are supported by the -mrtm and -mhle switches.

Last but not least, GCC 4.8 supports the Intel FXSR, XSAVE and XSAVEOPT instruction sets with -mfxsr, -mxsave, and -mxsaveopt.

Aside from advancing Intel's processor support, GCC 4.8 also offers AMD Jaguar and Steamroller support. Steamroller is "Bulldozer 3" and Jaguar is AMD's upcoming Fusion APU.

Other GCC 4.8 highlights include a new optimization level, some performance advantages, libstdc++ improvements, new optimizations, better C++11 support and early C++1y support, improved diagnostics, is built in C++ mode, and many other additions.

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Michael Larabel is the principal author of Phoronix.com and founded the site in 2004 with a focus on enriching the Linux hardware experience. Michael has written more than 10,000 articles covering the state of Linux hardware support, Linux performance, graphics drivers, and other topics. Michael is also the lead developer of the Phoronix Test Suite, Phoromatic, and OpenBenchmarking.org automated benchmarking software. He can be followed via Twitter or contacted via MichaelLarabel.com.

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