The open-source Radeon R600 LLVM back-end has finally received support for indirect memory addressing.
AMD's Tom Stellard put out the 1200 line patch today that enables indirect addressing support within the R600 LLVM GPU target. Indirect addressing support has been one of the major limitations so far in this Radeon LLVM back-end. This back-end can be optionally used by the R600 Gallium3D driver for its shader compiler and is a key requirement for the Radeon OpenCL/GPGPU compute support
. As far as end-users are concerned, the lack of indirect addressing support has made the LLVM back-end shader compiler not work for some OpenGL games like Unigine and Sauerbraten. (See Trying Out AMD's Radeon Gallium3D LLVM Compiler
Stellard writes in his mailing list message
that for now this indirect addressing is R600-only with the Radeon HD 7000 "Southern islands" implementation still missing a few callbacks used during this process. He additionally writes, "At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array."
The R600 LLVM GPU back-end was removed from Mesa
and merged into upstream LLVM
. This R600 LLVM indirect addressing support will soon likely be merged into Tom Stellard's R600 LLVM repository
followed by eventually making it into the next R600 GPU LLVM pull that should end up being released as part of LLVM 3.3 later this year.