The soon-to-be-released LLVM 3.2
compiler infrastructure will expand upon its coverage of processor support and CPU capabilities.
Some of the noteworthy improvements to the LLVM 3.2 processor/hardware support includes:
- Minor code-generation improvements for x86 and x86_64.
- With the x86/x86_64 improvements, there's particular improvements around LLVM's support for AVX2. The Advanced Vector Extensions 2, which will premiere with Intel's Haswell
processors next year, build upon the AVX support originally introduced in the Sandy Bridge processors. The additions found in Advanced Vector Extensions 2 / Haswell New Instructions include expanding most integer instructions to 256 bits, three-operand general-purpose bit manipulation and multiply, Gather support to enable vector elements to be loaded from non-contiguous memory, DWORD/QDWORD-granularity any-to-any permutes, vector shifts, and three-operand fused multiply-accumulate support.
- Better support for PowerPC
processors with LLVM 3.2.
- Support, including performance tuning, for the ARM-based A6 Swift processor. The A6 Swift is Apple's SoC found within the iPhone 5 that is twice as fast as the A5 ARM SoC.
- The LLVM ARM support now includes a full-featured macro assembler. This ARM integrated assembler has support for Thumb1/Thumb2/ARM modes along with VFP2, VFP3, and NEON extensions.
- The MIPS target improvements include integrated assembler support, fast calling convention, an Android MIPS tool-chain for Clang, a MIPS32/MIPS64 disassembler, experimental MIPS32 DSP intrinsics handling, experimental support for MIPS16, and improved register allocation.
Aside from the processor-specific work in LLVM 3.2, this compiler infrastructure update due out this month also features an automatic loop vectorizer
, Polly optimizations
, and other improvements to be talked about in future Phoronix articles.