Tilera TILE64 Back-End For LLVM Published
Written by Michael Larabel in Compiler on 06 September 2012 at 07:16 AM EDT. 2 Comments
Compiler
An LLVM back-end for Tilera's TILE64 processor has been published.

An LLVM back-end was released by a user for TILE64, the multi-core Tilera processor packing 64 tiles, a.k.a. a processor, cache, and non-blocking router. TILE64 builds upon a MIPS-derived VLIW instruction set with the processor itself targeting networking and digital video environments with high performance needs.

GCC has been supporting various Tilera CPUs, Linux has supported TILE64 since the Linux 2.6.36 kernel, and now support is being enabled within LLVM.

The LLVM back-end for TILE64 has yet to be merged but currently is living separately from the LLVM code-base. With the LLVM 3.1 back-end, it's a "minimalist functioning implementation." The developer, David Juhasz, is now working on utilizing LLVM's VLIW packetizer and making other improvements.

This work is being done out of the Eötvös Loránd University in Hungary. The LLVM/Clang TILE64 back-ends for LLVM 3.1 and an LLVM 3.2 SVN snapshot can be found here. Additional information is available from the LLVM development announcement.
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Michael Larabel is the principal author of Phoronix.com and founded the web-site in 2004 with a focus on enriching the Linux hardware experience and being the largest web-site devoted to Linux hardware reviews, particularly for products relevant to Linux gamers and enthusiasts but also commonly reviewing servers/workstations and embedded Linux devices. Michael has written more than 10,000 articles covering the state of Linux hardware support, Linux performance, graphics hardware drivers, and other topics. Michael is also the lead developer of the Phoronix Test Suite, Phoromatic, and OpenBenchmarking.org automated testing software. He can be followed via Twitter or contacted via MichaelLarabel.com.

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