Cyril Chemparathy of Texas Instruments describes on the kernel mailing list, "TI's scalable KeyStone II architecture includes support for both TMS320C66x floating point DSPs and ARM Cortex-A15 clusters, for a mixture of up to 32 cores per SoC. The solution is optimized around a high performance chip interconnect and a rich set of on chip peripherals. Please refer  for initial technical documentation on these devices."
TI's Keystone II should be interesting for ARM-based high performance computing. Texas Instruments has released some Keystone details via their web-site.
This initial TI Keystone Linux kernel support does handle SMP and LPAE boot and the other basics spread across 23 kernel patches, but is still early and TI is soliciting feedback.