Gallium3D's LLVMpipe Now Handles Wider Registers
If you have an AVX-enabled processor like Intel's Sandy/Ivy Bridge or AMD's Bulldozer, there's some good news should you be relying upon Mesa's Gallium3D LLVMpipe driver.
Jose Fonseca of VMware has been working on wider registers in LLVMpipe. While this CPU-based software driver now supports SIMD registers wider than 128-bits, Fonseca isn't reporting any improvements as a result.
The lack of performance improvements with this wider register support for the performance-friendly Gallium3D software rasterizer, according to Jose, is namely due to LLVMpipe being dominated by integer SIMD instructions while the current AVX1 instruction set instruments are for handling floating-point instructions. This may even cause some performance overhead.
While there may not be performance gains at the moment out of this CPU-based driver leveraging LLVM, it does provide some architectural benefits.
This code does better stress MC-JIT from LLVM, which should be better improved with the LLVM 3.2 release due out in a few months.
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