Gallium3D's LLVMpipe Now Handles Wider Registers
Written by Michael Larabel in Mesa on 18 July 2012 at 12:28 AM EDT. 4 Comments
If you have an AVX-enabled processor like Intel's Sandy/Ivy Bridge or AMD's Bulldozer, there's some good news should you be relying upon Mesa's Gallium3D LLVMpipe driver.

Jose Fonseca of VMware has been working on wider registers in LLVMpipe. While this CPU-based software driver now supports SIMD registers wider than 128-bits, Fonseca isn't reporting any improvements as a result.

The lack of performance improvements with this wider register support for the performance-friendly Gallium3D software rasterizer, according to Jose, is namely due to LLVMpipe being dominated by integer SIMD instructions while the current AVX1 instruction set instruments are for handling floating-point instructions. This may even cause some performance overhead.

While there may not be performance gains at the moment out of this CPU-based driver leveraging LLVM, it does provide some architectural benefits.

This code does better stress MC-JIT from LLVM, which should be better improved with the LLVM 3.2 release due out in a few months.
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Michael Larabel is the principal author of Phoronix.com and founded the site in 2004 with a focus on enriching the Linux hardware experience. Michael has written more than 10,000 articles covering the state of Linux hardware support, Linux performance, graphics drivers, and other topics. Michael is also the lead developer of the Phoronix Test Suite, Phoromatic, and OpenBenchmarking.org automated benchmarking software. He can be followed via Twitter or contacted via MichaelLarabel.com.

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