Intel Developers Looking To Get Nios II Backend In LLVM
Intel's compiler team is working on getting an Altera Nios II back-end mainlined within LLVM.
Nios II is a 32-bit general-purpose RISC processor part of the Altera family of FPGAs. Intel acquired Altera back in 2015 for those that forgot or didn't get the memo. The 32-bit Nios II is the successor to the original (16-bit) Nios. Nios II is licensed through Synopsys Designware for those wanting the architecture on ASICs.
Intel developers are now proposing a Nios II back-end for both the architecture's R1 and R2 ISAs. GCC already has supported Nios II while Intel developers have been getting the LLVM support going.
Those interested in embedded systems or Nios II specifically can learn more details about Intel's proposed LLVM back-end plans via this LLVM-dev message.
Nios II is a 32-bit general-purpose RISC processor part of the Altera family of FPGAs. Intel acquired Altera back in 2015 for those that forgot or didn't get the memo. The 32-bit Nios II is the successor to the original (16-bit) Nios. Nios II is licensed through Synopsys Designware for those wanting the architecture on ASICs.
Intel developers are now proposing a Nios II back-end for both the architecture's R1 and R2 ISAs. GCC already has supported Nios II while Intel developers have been getting the LLVM support going.
Those interested in embedded systems or Nios II specifically can learn more details about Intel's proposed LLVM back-end plans via this LLVM-dev message.
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