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Intel's New SNB Acceleration Architecture Still Maturing

Michael Larabel

Published on 31 August 2011
Written by Michael Larabel
Page 1 of 6 - 8 Comments

In early June there was the introduction of the Sandy Bridge New Acceleration Architecture by Intel that dramatically excelled the 2D and 3D performance of their processor graphics on their Sandy Bridge hardware along with previous-generation IGPs. Here is a look at how the SNA acceleration architecture is performing today.

When Sandy Bridge New Acceleration was pushed to the xf86-video-intel public Git repository, it was quick to advance to address bugs and other regressions compared to their previous UXA implementation. Benchmarks from July on Phoronix indicated some performance improvements, in line with Intel's claims about some workloads being tremendously faster using the SNA back-end.

SNA is not the default, however, when building the xf86-video-intel DDX as there are still a few outstanding bugs. The new acceleration architecture needs to be manually enabled via passing the --enable-sna argument when building the Intel X.Org driver. Being reported to the Xorg.0.log when using the Intel DDX will be a line indicating the SNA Sandy Bridge back-end is in use.

With it being a while since delivering the last SNA-focused benchmarks, this morning I produced some new tests using the latest Git code. Intel Core i3 2120 and Intel Core i5 2400S reviews are being worked on for publishing next month, per the upcoming Oktoberfest articles mentioned this morning. After the Core i5 2400S Ubuntu testing was done, the xf86-video-intel DDX Git was rebuilt with the --enable-sna option. Mesa was using 7.12-devel Git as of last night and there was the latest Linux 3.1 kernel snapshot.

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