Pmdata and CareyM found out bugs in renouveau, which were leaking giving error / incorrect result for certain tests. CareyM even went back to driver versions 71xx to make sure it was not a bug in the driver (Thanks a lot for this hard work!). Later pmdata found the culprit An Enable(GL_TEXTURE_RECTANGLE_NV) where it was not needed. He rewrote the test to squish this bug (Patch).
Stillunknown along with various contributors tried to get mode switching into shape. Chowmeined had problems with incorrect timing leaving two pink lines at the bottom and right side of the display. He managed to eliminate those at the bottom but failed to fully get rid of the one on the right. Stillunknown tested supplied test patches and got it into a working state.
Later malc0 joined the scene with a patch to parse the DCB in the video card bios. Furthermore, the DDX saw many clean ups to the RandR 1.2 and related code, so that development and maintenance should become easier.
Display Configuration Block (DCB)
The DCB is a part of the video card's bios and consists of a number of entries which include data interesting for mode setting. Each entry relates to a potential (possible) output like VGA, TV-OUT etc. Currently nouveau uses the data associated with the entries to know what output types are present, what I2C ports to use to get EDID data for each output and how the RAMDAC routing should be performed.
Pq did some testing on NV20 and supplied further information about his results. Fiddling with various timing registers both managed to get NV20 into a working state too. IRC.
jb17some presented his reverse engineering work on XvMC. He seems to be sure that he now understands the basic way of working. The FIFO sets up and controls rendering as usual, but the data is not uploaded via FIFO but via a separate buffer. This buffer is created / updated via calls to XVMCCreateContext(), XVMCCreateSurface(), XVMCRenderSurface(). Whether he intends to give an implementation, a shot remains to be seen. IRC.
With work on NV3x finished and marcheu fixing some of the remaining NV30-only bugs, jkolb set his eyes on a new challenge. After talking to marcheu, airlied and darktama he decided to work a bit on Gallium and TTM. JKolb did a couple of commits, first some stub BO driver functions that did nothing, then fleshed out a bit from airlied's Radeon TTM code. At that point, darktama send jkolb a diff of his TTM branch, and he added some bits from that code that were missing from the BO driver, and committed darktama's fence driver. At that point, Darktama did a bit of work at fixing a few bugs which were found compared to the original code.
To get a fleshed out Gallium3d / TTM framework much is missing though. The DRM is still missing some vital pieces ("superioctl", some bad bugs, etc), and we have our entire userspace code to adapt. This is actually quite a lot of work!
By the way: airlied has posted the new DRM including TTM to the LKML. That means that the API should be finished and as stable as it can get under Linux.
So we now "only" need to flesh out the parts that are driving the 3D engines on the cards. This sounds much easier than done though, as marcheu needs to get his generic part on Gallium3D done, so that older cards without variable length shaders can handle the requests too.
Some short topics:
· We are looking for someone to write a "Do notifiers in AGP space work?" test for nouveau. Should the notifier not work, nouveau should use notifiers a PCI space. Basically, pq and marcheu are both occupied but this patch would help quite a bit.
· Our code style policy is: Indent via tabs eight characters wide and additional spaces if indentation is smaller than eight characters (counted from the last tab on the line).
· The documentation of Xv for mmio-parse register was enhanced by hkBst.
Please do test whether Nouveau PPC on PPC works for you (in case you have that kind of hardware).
Additionally, please have a look at the "Testers wanted" page for requirements coming up between our issues.
Finally, thanks to Luc Vernerey for sending us two cards (GeForce 3 and 4).
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