Intel Working On 5-Level Paging To Increase Linux Virtual/Physical Address Space
Intel developers are working on "five level paging" to overcome the x86_64 limitation of 256 TiB of virtual address space and 64 TiB of physical address space. While you may not have that much memory in your desktop, that limitation is being hit but can be increased through 5-level paging.
Upcoming Intel hardware supports 5-level paging, which is an extension to the page table structure by adding another layer of translation. With 5-level paging the virtual address space goes from a 256 TiB maximum to 128 PiB while the physical address space threshold goes from 64 TiB to 4 PiB.
This big set of patches to increase the virtual/physical address space capabilities of the Linux kernel for future Intel x86_64 hardware can currently be found via this kernel mailing list thread. Intel's 5-level paging design is explained in more detail via this PDF white paper.
Upcoming Intel hardware supports 5-level paging, which is an extension to the page table structure by adding another layer of translation. With 5-level paging the virtual address space goes from a 256 TiB maximum to 128 PiB while the physical address space threshold goes from 64 TiB to 4 PiB.
This big set of patches to increase the virtual/physical address space capabilities of the Linux kernel for future Intel x86_64 hardware can currently be found via this kernel mailing list thread. Intel's 5-level paging design is explained in more detail via this PDF white paper.
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