Announcement

Collapse
No announcement yet.

AMD FX-4100 Bulldozer

Collapse
X
 
  • Filter
  • Time
  • Show
Clear All
new posts

  • #51
    A Core is a single CPU. Period. If the design is so interwoven and shared that it can't be split up without evening out all modules; it's a single core.

    So this AMD is a dual-core CPU.

    Instructions might take more clock cycles to complete the logic operation, but it might be more efficient in that it can do more instructions per clock on avarage.

    What we're discussing is nothing but two identical CPU's that have dual integer modules (I still have to read up about that, will do).

    Given that most desktop stuff doesn't require insane amounts of floats per integers (less than 0.5); it's great and cheap. It's also great and cheap for home servers. Gaming not that much (if you buy the latest GPU's).

    I personally don't like this path, because float is already slower than integer. AMD now cut down the difference even further. This sucks balls. Short term decisions.

    Comment


    • #52
      By that definition, then a core on BD is not the same thing as a core on every other x86 architecture being used. On BD a so called core doesnt have a front end, or a FP unit, or a retirement stage, or a cache heirarchy.... No it just does not make any sense.

      A module is a dual processor core. A module is not a dual core processor.. It may seem like semantics to some, but I think it is a very important differentiation.

      Comment


      • #53
        Floating point is freaking part of the CPU. Given that there are two, it's dual core. Unless you have four cores and two different ones at that.

        The term dual-core was invented for essentialy two CPU's being molten together on one die. In this case it's not any different. Unless it's a six core having four integer and two float cores. But they are not exactly entire seperate, so I'll simply calll this dual core.

        Comment


        • #54
          While some argue about the semantics, I hope others are optimizing software for the architecture

          Comment


          • #55
            Originally posted by PsynoKhi0 View Post
            While some argue about the semantics, I hope others are optimizing software for the architecture
            Now that's a problem.

            You see the point is that only big ass problems require the entire CPU. The rest is wasting thread start, lock, sync and stop. That's cool and all when you make GUI apps (multithread programming is a bliss there (and also in general)), but you're wasting resources for the enduser, not for yourself.

            I see my computer as a computer, not a kitchen apparatus. Therefore I want enormous power. Not because I'm a lazy programmer, but I tend to find resource restrictions problems fascinating. Floating point is kind of a requirement for visual and audio problems.

            This CPU just made floating point operations at least four times more expensive than integer operations. Vincent does not like.

            Comment


            • #56
              Q, I belive you confuse hyper threading (which seriously must die at once, unless you're using a server, maybe) with assembly order problems, x86 to RISC translation and got it all messed up and backwards.

              Comment


              • #57
                may be the bulldozer should have been created with 2 cpu + 1 fpu + 1 cl_gpu
                with cl_gpu i mean only the elements of gpu that do the opencl and absolutely not a full gpu in the cpu .
                may be like that this cpu would have been better than that . by the way the gap is not that far between number 1 in results and this one that is the lowest Mhz model

                Comment


                • #58
                  Originally posted by V!NCENT View Post
                  Floating point is freaking part of the CPU. Given that there are two, it's dual core. Unless you have four cores and two different ones at that.

                  The term dual-core was invented for essentialy two CPU's being molten together on one die. In this case it's not any different. Unless it's a six core having four integer and two float cores. But they are not exactly entire seperate, so I'll simply calll this dual core.


                  The term dual core was invented because there was actually 2 cores on one die. In BD case a module does not have 2 cores. It has 2 integer processors and one independent floating point processor. In BD the FP processor was decoupled from the pipeline to allow it to be shared. BD architecture is NOT the same as older generations, it cannot be compared as such. ... If you wanted to continue using your method of reasoning, it still wouldnt be a dual core, it would be an asymmetric tri-core.... But then what is the front end? Whats the cache heirarchy? What do you call them? Are they also cores?

                  If we take as an example of what a core is in older generations, then a module -is- a core.
                  Last edited by duby229; 23 October 2011, 12:22 AM.

                  Comment


                  • #59
                    Originally posted by jcgeny View Post
                    may be the bulldozer should have been created with 2 cpu + 1 fpu + 1 cl_gpu
                    with cl_gpu i mean only the elements of gpu that do the opencl and absolutely not a full gpu in the cpu .
                    may be like that this cpu would have been better than that . by the way the gap is not that far between number 1 in results and this one that is the lowest Mhz model
                    That would be stage3 Fusion. AMD is currently working on it. Stage2 Fusion is what AMD has on the market now with the APU's based on Stars cores, and also the APU's that will be released based on BD cores. Stage1 Fusion was never released as a commercial product.

                    EDIT: Take a look at how the BD architecture decoupled the FP pipeline from the Integer pipelines, and made the frontend unified across them... Integrating a GPU's processing elements into a module is possible, which will likely be done as a replacement for the existing FP pipeline. This means that existing instruction sets will be supported, but to take full advantage of instruction parallelism a new instruction set will need to be written to take advantage of it in general purpose software..

                    EDIT2: Worth noting, stage3 fusion is still probably 4-5 more years away.
                    Last edited by duby229; 23 October 2011, 12:34 AM.

                    Comment


                    • #60
                      Originally posted by duby229 View Post
                      EDIT2: Worth noting, stage3 fusion is still probably 4-5 more years away.
                      How do you know that?

                      Comment

                      Working...
                      X