Updated AMD Microcode Fixes The R7 260X, Other "SI" GPUs
Phoronix: Updated AMD Microcode Fixes The R7 260X, Other "SI" GPUs
Alex Deucher sent out a set of three patches today to update the microcode used by the AMD "Southern Islands" graphics processors...
Getting an r9 270 today, should I expect bad performance without this patch?
Only certain r7 260x cards seems to be affected. I haven't seen any reports of problems on SI boards.
Originally Posted by peppercats
Too bad we can't fix it by ourselves.
does this affect the apus, those with r7 gpus?
Maybe or maybe not, at least I am still waiting for the R7 support to land into Fedora 20 to get it working at all:
Originally Posted by Yorgos
Only dGPUs; APUs don't have a gddr5 memory.
Originally Posted by Yorgos
Hey Alex, do you know how expensive GDDR5 memory is? Like would it be impossible to make an APU revision that had lets say 1Gb of GDDR5 memory integrated? Seems like a good fit for HSA.. 1GB gets used up first, then the GPU starts using system RAM. Maybe use the 1GB of a cache? Most commonly accessed textures get loaded there.
Originally Posted by agd5f
Just spitballing, I don't know how fast GDDR5 memory is compared to DDR3 as far as clockspeeds go. If GDDR5 is only running at lets say 4000mhz then its pointless because DDR4 is defaulting to 2000mhz and it could prob get overclocked to 4k in time
1GB of memory would just take up too much space on the die. Look at Intels Crystalwell, they implemented it as a seperated soldered die for HD5200 parts, it would add 1/8 the size of the die to the chip, albeit it is a higher speed memory than classic ddr capacitor based ram, and has a more complex layout, so it certainly uses more physical die per allocatable bit (on modern high end ddr3 ram, the memory controller usually uses more space than the actual capacitors). Another good example is the soldered on memory you find on GPUs - here is a 290x's PCB, which has 16 256MB chips soldered around the GPU core. So you would want four of those embedded in the CPU itself, which is prohibitive size-wise. You could get them smaller than that, but you would need to expand the physical die quite a bit.
Originally Posted by Ericg
L3 cache already occupies upwards of a sixth the die a modern Intel chip - for upwards of 16 - 32MB of cache. Memory just takes up a lot of room.
You could solder a gig of gddr5 to a board, probably, and use that, but that kind of defeats the purpose of HSA. What you would probably end up doing is some NUMA driver to have high bandwidth and low latency memory available and load balance accordingly in an HSA world, but really like you said, DDR is getting fast enough, especially in the DDR4 lifetime, we shouldn't add that unnecessary complexity, and if anything just add l3 and l4 caches.
Last edited by zanny; 04-11-2014 at 04:29 PM.
AMD teamed up with Hynix to make stacked memory a possibility to replace GDDR5. I would figure that they are going to release an APU with this stacked memory in the future, perhaps even completely demolishing the need for RAM DIMMs.
Originally Posted by zanny