AMD "Kaveri" APU Linux Review, Benchmarks Next Week

[unl34shed]

Yes.

Thank you

[atcrank]

questions for kaveri testing

Hi michael - thanks for taking this on.

I am interested in a kaveri box doing some htpc, some file serving, a fair amount of idling and occasionally playing games. I currently have a 7790. So I would like to know:

• Driver support for VDPAU and other video playback features (shader based deinterlacing is one, I think?), is it working?
  Driver support for Dual Graphics, and if there's a benefit (toms hardware found that there was a nominal fps improvement but that it was not real - is it possible in linux? If possible, does it help?
  Power consumption for idle, file serving, transcoding, gaming (or equiv). Only need some point measures at the wall, time history not needed. AMD have claimed lower idle power than Intel - does Linux produce this too?
  Would like to know more about binaries - I would expect every program would need to be recompiled to maximize use of the resources on the chip - is this true? Are the compilers ready?

Others have mentioned many of these, and most are not really benchmarks, just checks for what works, and how hard it is to make it work.

[curaga]

I wonder if there are any tests that can show HSA in action.

[juanrga]

I will be anxious to see Kaveri benchmarked and compared to i5s. Some time ago I did a simulation







The rest here

http://www.brightsideofnews.com/news/2013/11/4/what-to-expect-from-kaveri-a-detailed-predictive-analysis.aspx

http://juanrga.com/en/AMD-kaveri-benchmark.html

I wrote that before APU13. I assumed a 4GHz Kaveri and 20% IPC, but A10-7850k clock is 3.7GHz. Some leaked benchmarks suggest that IPC gain is larger (30%) and others suggest the contrary.

[fteoOpty64]

[QUOTEhttp://juanrga.com/en/AMD-kaveri-benchmark.html

I wrote that before APU13. I assumed a 4GHz Kaveri and 20% IPC, but A10-7850k clock is 3.7GHz. Some leaked benchmarks suggest that IPC gain is larger (30%) and others suggest the contrary.[/QUOTE]

Even with AMD claiming IPC improvement, I think because the Memory controller is now different, there seems to be additional latency/blocks impose by the HSA Xbar switch. In the Kaveri implementation, the Xbar connects to ALL compute units which means more than 3X the number of interconnects as previously (was 4 for 4cpu cores, now 12 for 12CUs). At the same time, coherency and ownership needs to be managed for each CU in their respective memory spaces. Shared FB has many to many connects. So this Xbar is rather complex and is show in the die-shot of significant size almost as big as the L2 cpu caches combine!. {ie if you consider the Xbar and the memory controller on the cpu side as well, I call it the hUMA Block}
This part is certainly a well kept trade secret as it is the main new IP of this architecture.

In some Kaveri ram benchmarks I see very little gain going from 2133Mhz Ram bus to 2400Mhz, indicating a limitation in scaling, hence potential complexities of the Xbar in terms of direct path (we tend to think that but I do not think it is as direct). AMD is not known for its memory controller design, so future evolution might improve.