Greetings! I have reviewed all open documents and found no mention of the PLL registers, which are responsible for pixelclock. For example EXT1_PPLL_POST_DIV - one of them . They are still under the NDA? But it without them not to setvideomode ... Whether documentation in the future?
Announcement
Collapse
No announcement yet.
Open documentation...
Collapse
X
-
Originally posted by OleSt View PostGreetings! I have reviewed all open documents and found no mention of the PLL registers, which are responsible for pixelclock. For example EXT1_PPLL_POST_DIV - one of them . They are still under the NDA? But it without them not to setvideomode ... Whether documentation in the future?
-
Originally posted by OleSt View PostYes, I saw them there. Just interesting, this NDA or simply forgotten to provide documentation. Thanks for your reply .
Comment
-
Yep. In order to get the project moving more quickly we started with some already-sanitized documents which (in theory) covered all the registers needed for modesetting. The Novell developers found a number of areas missing so as each gap was discovered we collected the information and sent it across via email or a small doc for a specific set of registers. There are probably 50 of those "doc-lets" which we have to collect, clean up, review, and turn into a real document.
My current thinking is to do that after R6xx 3D documentation is released, but if anyone has specific questions they can email us at the address on the Open GPU Documentation page at amd.com.Test signature
Comment
Comment