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Thread: Tilera Publishes TILE-Gx CPU Back-End To LLVM

  1. #1
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    Default Tilera Publishes TILE-Gx CPU Back-End To LLVM

    Phoronix: Tilera Publishes TILE-Gx CPU Back-End To LLVM

    After already having integrated TILE-Gx support into GCC 4.7, Tilera is now calling for the mainlining of its TILE-Gx back-end into LLVM. The LLVM Tile-Gx back-end is needed for the company's forthcoming many-core processor...

    http://www.phoronix.com/vr.php?view=MTMxNTk

  2. #2
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    Can anyone give a simplified explanation as to the difference between this CPU architecture and the Parrallella?

  3. #3
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    Default @FiL

    The Parallella is an ARM processor with 16 or 64 FPU's and the TileX has it's own ISA and each core is a complete superscalar CPU.

  4. #4
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    Default Wasn't (one) of the Tilera processors MIPS based?

    Quote Originally Posted by shaunehunter View Post
    The Parallella is an ARM processor with 16 or 64 FPU's and the TileX has it's own ISA and each core is a complete superscalar CPU.
    Wasn't one of the Tilera processors based around many MIPS cores?

    Is this one similar or is it a totally different ISA?

  5. #5
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    Quote Originally Posted by bms20 View Post
    Wasn't one of the Tilera processors based around many MIPS cores?

    Is this one similar or is it a totally different ISA?
    The microcode was described as MIPS like in a couple news stories but it's a VLIW processor. MIPS doesn't have them listed as a licencee either.

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