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Thread: AMD FX-4100 Bulldozer

  1. #41
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    Quote Originally Posted by Michael View Post
    There's new registers on the 15h/Bulldozer parts to be able to measure current power usage for the CPU itself, and the Phoronix Test Suite is now able to monitor that during tests.
    Well it allows you to measure "estimated" current draw. It operates much the same as how the thermal sensing in the AMD Phenoms work where it doesn't give the true temperature but a calculated difference from nominal.

  2. #42

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    Quote Originally Posted by Michael View Post
    There's new registers on the 15h/Bulldozer parts to be able to measure current power usage for the CPU itself, and the Phoronix Test Suite is now able to monitor that during tests.
    Interesting. And that shows the TDP exceeded continuously? Short term is also a turbo mode feature.

  3. #43
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    Quote Originally Posted by Qaridarium View Post
    i do not understand the word "chit" do you mean shit?




    8 integer ALUs sound like a 8 core cpu but the 4 core intel cpus also do have 8 integer ALUs.

    also i 4*128bit FPUs and 4*256bit SIMD units.

    The SIMD units tells us 4 core for the FX8000 and the FPU couns also 4.

    the FX4000 is a dualcore in AVX256bit and its a dualcore in Floadingpoint Calculation and its a Dualcore in Integer to if you count the overall Integer units in an intel CPU because there are 2 integer units per intel core. FX4000 integer count=4 intel dualcore integer count=4

    it is a dualcore in all criteria.
    I dont think your understanding whats going on here....

    Hyperthreading uses a method of multhreading called SMT, which stands for Symmetric MultiThreading The front end is capable of decoding up to 4 instructions per cycle. Those 4 instructions can be either from a single thread or from 2 threads. They then get fed into an instruction scheduler that issues the instructions into a set of ALUs and AGUs... This is a SINGLE superscaler pipeline.

    BD architecture uses a method of multithreading called SMP, which stands for Symmetric MultiProcessing. The front end is capable of decoding up to 4 instructions per cycle. Those 4 instructions can be either from a single thread or from 2 threads. Then instructions from the first thread are fed into the instruction scheduler for the first int processor, and instructions from the second thread get fed into the instruction scheduler for the second int processor. Floating Point instructions, regardless of which thread it came from are fed into a dedicated scheduler for the FlexFP Pipeline. Per -thread- there will be 2 pipelines used, 1 for integer instructions and 1 for floating point instructions, but they work together as a single superscaler pipeline. Per -module- there will be 3 pipelines used, 2 int pipelines, one for each thread, which both share 1 fp pipeline, but they function independently as 2 superscaler pipelines.

    Sandybridge does --NOT-- have 2 int pipeline per core. Also you are using the term ALU wrong. It stands for Arithmetic Logic Unit.. Of these each core on sandybridge has a variety of different types. It has 3 different types of int ALUs --per-- core. Each one is used for executing different types of integer instructions. The SIMD units are used for FP operations.

    BD has 2 int pipelines per module. Each pipeline has 2 int ALUs. Both of the are mostly identical, though they do have some small differences. Keep in mind that each thread only has access to -ONE- pipeline, so per thread only 2 ALUs.

    Hope this clears up some of your confusion. Though I understand this stuff, I'm not very good at describing it... Here are some of the best descriptions I've found. Please take the time to read them so you can improve your understanding.

    Sandy Bridge Architecture. http://realworldtech.com/page.cfm?Ar...1810191937&p=1
    Bulldozer Architecture http://realworldtech.com/page.cfm?Ar...WT082610181333
    Last edited by duby229; 10-19-2011 at 08:47 PM.

  4. #44
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    Quote Originally Posted by duby229 View Post
    I dont think your understanding whats going on here....
    your thinking is wrong i know this ALL but you don't understand my argument my argument is about the practice.
    there is no difference for the software if there is a longer pipeline splits up by hyper-threating compared to 2 shorter pipelines.
    the Core- I3 act like a quatcore but it isn't a quatcore and the FX4000 act like a Quatcore but it isn't a quatcore.
    an actor isn't a real one.
    it doesn't matter if a Actor use the technique SMT or the Actor used the technique SMP
    the I3 is a dualcore Actor imitate a 4core cpu with SMT
    the FX4000 is a dualcore Actor imitate a 4core cpu with SMP.
    for the consumer there is no difference for multi-core applications.

  5. #45
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    EDIT: damn edit limit, even increased I still run into it....

    I wanted to try and clear up what I was saying about pipelines... The front end of an architecture basically ends after the instructions are decoded and stored in the instruction que. Then the backend starts. In Sandybridge, there is only -1- instruction scheduler which issues instructions to execution units regardless of whether they ae from the first thread or the second thread, or whether they are fp or integer... In Bulldozer there is -3- instruction schedulers, 1 for each integer processor, and 1 for the floating point processor.

    That is why I do -NOT- consider a bulldozer module as 2 cores. if AMD wanted to use that terminology then it should have been called 3 asynchronous cores. But, functionally it takes 1 bulldozer module to equal the capability of 1 sandybridge core, so in the sense of what Intel calls a core, then it would take a full module to be a core.

    SO IF 1 MODULE = 1 CORE THEN 1 MODULE IS 1 CORE

    FX-4000 series = 2 modules with 4 Int processors and 2 FP processors
    FX-6000 series = 3 modules with 6 Int processors and 3 FP processors
    FX-6000 series = 4 modules with 8 Int processors and 4 FP processors
    Last edited by duby229; 10-19-2011 at 09:20 PM.

  6. #46
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    Quote Originally Posted by Qaridarium View Post
    your thinking is wrong i know this ALL but you don't understand my argument my argument is about the practice.
    there is no difference for the software if there is a longer pipeline splits up by hyper-threating compared to 2 shorter pipelines.
    the Core- I3 act like a quatcore but it isn't a quatcore and the FX4000 act like a Quatcore but it isn't a quatcore.
    an actor isn't a real one.
    it doesn't matter if a Actor use the technique SMT or the Actor used the technique SMP
    the I3 is a dualcore Actor imitate a 4core cpu with SMT
    the FX4000 is a dualcore Actor imitate a 4core cpu with SMP.
    for the consumer there is no difference for multi-core applications.
    No you clearly dont know what your talking about. You REALLY SHOULD read the articles I posted.

    No SMT does -NOT- make the I3 that was used into a 4 core... It -IS- 2 cores.

    Now I agree that AMD marketed BD incorrectly, but it has -NOTHING- to do with SMT. Instead it has -EVERYTHING- to do with funtionality... And int pipeline doesnt do any decoding... An int pipeline doesnt process fp instructions... It takes a module to be a functional device, therefore a module is a core.
    Last edited by duby229; 10-19-2011 at 09:24 PM.

  7. #47
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    Quote Originally Posted by duby229 View Post
    No you clearly dont know what your talking about. No SMT does -NOT- make the I3 that was used into a 4 core... It -IS- 2 cores.
    Now I agree that AMD marketed BD incorrectly, but it has -NOTHING- to do with SMT. Instead it has -EVERYTHING- to do with funtionality... And int pipeline doesnt do any decoding... An int pipeline doesnt process fp instructions... It takes a module to be a functional device, therefore a module is a core.
    i think you are blinkered because of your technical skills.
    open our eyes if a intel dualcore beats an FX4000 quatcore or it brings the same result then you are wrong in practice.
    you are only right in an theoretical point of view in the practice you are wrong.
    the I3 and FX4000 are Actors and they play the act "Quatcore" and the result is nearly the same.

  8. #48
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    No it isnt nearly the same. AMD's architecture has 2 int pipelines and 1 floating point pipeline per module. It is not the same. Software will -NOT- behave the same.

    You REALLY SHOULD read the articles I posted.
    Last edited by duby229; 10-19-2011 at 09:37 PM.

  9. #49
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    Quote Originally Posted by duby229 View Post
    No it isnt nearly the same. AMD's architecture has 2 int pipelines and 1 floating point pipeline per module. It is not the same. Software will -NOT- behave the same.
    You REALLY SHOULD read the articles I posted.
    if you have the double long pipe line software emulated(hyper-threating) splits into 2 pieces )intel i3( its the same compared to 2 half long pipe lines.
    because of this the benchmarks nearly the same.
    Intel wins if more single threated performance is needed and amd wins if more multi-task performance is needed.
    and i don't have to read your posts again because your posts chance nothing about my argumentation.

  10. #50
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    Quote Originally Posted by Qaridarium View Post
    if you have the double long pipe line software emulated(hyper-threating) splits into 2 pieces )intel i3( its the same compared to 2 half long pipe lines.
    because of this the benchmarks nearly the same.
    Intel wins if more single threated performance is needed and amd wins if more multi-task performance is needed.
    and i don't have to read your posts again because your posts chance nothing about my argumentation.
    This is a strange form of logic. What does benchmarking have to do with anything? We don't call Sandy Bridge a 25 core chip just because it performs 25 times faster than a 486DX. (Just a random number there, I'm not sure what the actual comparison would be). We look at the actual hardware and what it provides, not benchmarks.

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