from evergreen hardware:
- acronyms:
- HDP? Something dealing with the memory controller, tiling stuff?
- .rlc in the firmware name? rlc is related to interrupts.
- MC_VM_MD_* MC = Memory Controller VM = Virtual Memory MD = ?
- MC_VM_MB_* MC = Memory Controller VM = Virtual Memory MB = ?
- What is the mapping of the BAR0 aperture? Programming the MC/VM/PCI-E won't affect it? If BAR0 is hardcoded to VRAM, the first 256kB are for VGA, can we reclaim it? If yes, how to do it in a safe way?
- What is the max size of a page table for the PCI-E DMA aperture (GTT)?
- What is the use of page entry attribute SYSTEM and SNOOPED (vga?)?
- In register VM_CTX0_PROTECTION_FAULT_DEFAULT_ADDR, we write the gpu page index of the dummy page bus address (<< 12). That would mean linux must allocate bus addresses based on gpu page size alignment. Is linux kind of told about this thanks to PCI-E cache line size? That would be the same for PTEs. Bus addresses must be aligned on gpu page size. I know it works since GPU page size and x86-64 base page size are both 4kB but...
- Must AGP be disabled on PCI-E boards?
Comment