writing to IH/CP registers before micro-code is loaded

[sylware]

During device initialization, the device should be quiesced without any interrupts pending.

In the evergreen code path, the IH (Interrupt Handler), IH_RB (interrupt Handler Ring Buffer) and CP (Command Processor) registers are accessed in order to disable/reset interrupts before request_irq is called. But since micro-codes are not loaded, is that going to be effective?

[bridgman]

During device initialization, the device should be quiesced without any interrupts pending.

In the evergreen code path, the IH (Interrupt Handler), IH_RB (interrupt Handler Ring Buffer) and CP (Command Processor) registers are accessed in order to disable/reset interrupts before request_irq is called. But since micro-codes are not loaded, is that going to be effective?

agd5f would know better, but normally there is some random logic in the interrupt paths to store interrupt requests, then the state machines can turn internal interrupt bits on once the microcode is loaded. I imagine these writes are just to make sure that no interrupt bits came up "interrupting" after reset.

[agd5f]

During device initialization, the device should be quiesced without any interrupts pending.

In the evergreen code path, the IH (Interrupt Handler), IH_RB (interrupt Handler Ring Buffer) and CP (Command Processor) registers are accessed in order to disable/reset interrupts before request_irq is called. But since micro-codes are not loaded, is that going to be effective?

The mmio CP/IH control registers are independent of the ucode. It's just making sure they are off.

[sylware]

thx again!