Originally posted by chithanh
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Anyway, based on what I see in the wiki, the MXU unit only has 32-bit registers, which puts it roughly into the same category as the MIPS DSP ASE or ARMv6 SIMD. This is not impressive at all. For comparison, modern ARM processors have much wider 128-bit NEON registers, which are much better suited for graphics/multimedia heavylifting.
It lists onlx MXU ASE, but that could be due to the kernel not having detection for other ASEs implemented. Or maybe the SoC doesn't support them after all.
Was the system using a recent linux kernel? At least this CPU should support mips32r2 instructions, but such information does not seem to be properly listed and the following mips32r2 runtime detection code would not work right.
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