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    I didn't export any yet. It's a possible future...

    I didn't export any yet. It's a possible future use. We currently export the harvest information separately via the info ioctl.
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    I don't think the OEMs always set up the internal...

    I don't think the OEMs always set up the internal thermal sensor properly on APUs. They often use OEM specific sensors which seems to be the case on your board.
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    I don't think there is a good standard...

    I don't think there is a good standard cross-vendor way to expose this information. It's all VERY asic specific. Making it generic enough to support multiple vendors would really reduce the...
  4. Feel free to ping the list again. Sometimes...

    Feel free to ping the list again. Sometimes things fall through the cracks.
  5. How about this one? ...

    How about this one?

    http://www.newegg.com/Product/Product.aspx?Item=N82E16814129274
  6. You can drive up to 6 displays depending on the...

    You can drive up to 6 displays depending on the asic on all radeon GPUs since evergreen.
  7. With this set of patches all chips that support...

    With this set of patches all chips that support UVD are now supported, except the old RV550 cards which, may work with the r6xx UVD code if someone wanted to play with it. The RV730 has had UVD...
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    I'm not sure how you could improve the memory...

    I'm not sure how you could improve the memory reclocking. Memory reclocking has to be done during the vblank period to avoid display glitches during the reclock. With multiple monitors, the vblank...
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    What kernel are you using? That was fixed a...

    What kernel are you using? That was fixed a while ago. It now shows the actual adjusted state not the base state.
  10. No. rs780 and rs880 are 6xx based.

    No. rs780 and rs880 are 6xx based.
  11. Please read this thread again. All 6xx asics and...

    Please read this thread again. All 6xx asics and rv770/790.
  12. Christian's patch to disable interop on chips...

    Christian's patch to disable interop on chips that don't support field based decode just hit git today:
    http://cgit.freedesktop.org/mesa/mesa/commit/?id=12fb74fe895fe9954df127ca0ec6e4422fffb156
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    It polls the 3D/compute status registers...

    It polls the 3D/compute status registers directly. Ideally we'd expose those status registers via debugfs rather than making the application poll them directly. As for the GPU temperature, it's...
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    You need to use something like radeontop for load.

    You need to use something like radeontop for load.
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    You can see the current GPU power state (clocks,...

    You can see the current GPU power state (clocks, voltages, etc.) in /sys/kernel/debug/dri/64/radeon_pm_info
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    on r3xx+ it was shaders. On r1xx/r2xx there was...

    on r3xx+ it was shaders. On r1xx/r2xx there was a special MC mode you could enable in the 3D engine.
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    The bigger issue is that gallium still needs some...

    The bigger issue is that gallium still needs some fixes for big endian.
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    The mpeg MC block is just shaders. There is no...

    The mpeg MC block is just shaders. There is no special hw.
  19. Are you sure you don't have a gddr5 HD6450?

    Are you sure you don't have a gddr5 HD6450?
  20. Sorry, to disappoint you, but it appears UVD 2.1...

    Sorry, to disappoint you, but it appears UVD 2.1 does not support field based decode. I just tested it on my rv770 and it works fine, but only if you apply this mesa patch:...
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