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  1. Replies
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    my opinion

    The c++ benefits does not compensate for its technical cost. Then, better stick to C.
  2. Replies
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    Well... I understood that you must be very...

    Well... I understood that you must be very carefull with the render task and the load task. Indeed, you must keep the vram bandwidth and the caches for the render to be the most efficient. Loading...
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    Really... those close source drivers which Linus...

    Really... those close source drivers which Linus T. tolerates start to be a pain for everybody. Really. We need ultra high performance GNU GPL drivers for Linux and for *GOOD*. The DRM(BSD)/Mesa(MIT)...
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    complexity

    Last time I compared opengl3 with opengl4, I think I noted than opengl4 was simpler than opengl3 for the good reasons. Regarding opengl ES 2, I though about it like it was opengl as it was supposed...
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    Gpl symbols

    The GNU GPL Licence is not an GNU Library GPL Licence.
    You can check the licence file at the top of the linux tree. The only linux exception to the GNU GPL is for "normal" programs (no hardware...
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    Sticky: Thought all significant devs were north america...

    Thought all significant devs were north america based!

    my bad...
  7. Replies
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    95,937

    Sticky: What I wanted to say is: due to the time lag (I'm...

    What I wanted to say is: due to the time lag (I'm UTC+1), IRC is quite less convenient than a mailing-list to replace those forums for such questions.
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    Sticky: Indeed, and the site allows google to search...

    Indeed, and the site allows google to search those logs.

    Cool.

    The hard part for irc: the lag, because I'm UTC+1.

    Then it would be nice to have a mailing list... (not the global dri one, one...
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    Sticky: Indeed, but do we have a search historic for such...

    Indeed, but do we have a search historic for such questions on IRC?

    Because this forums track questions/answers, are public and are searchable.
  10. asked VESA...

    ... but they prefer to let the PCI-SIG define the interfaces.
  11. Replies
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    damn!

    Got a reply from samsung support: no 3D over displayport!

    It seems that monitors with 3D support over displayport do *not* exist!!

    Really, better go straight to external PCI-E with VESA...
  12. Replies
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    Well, I asked samsung about their support of...

    Well, I asked samsung about their support of stereo DP stream on that monitor.
    Let's wait and see. It seems it is the only displayport 3D monitor (haven't looked deep on the internet though).
    ...
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    I don't understand, there is only two methods for...

    I don't understand, there is only two methods for 3D over DP: progressive video and interlaced video (see stereo video attribute in misc1 main stream data attribute).
    I'm not interested by...
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    Thx a lot. I wait for your feedback on that...

    Thx a lot. I wait for your feedback on that question.
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    dce4 and displayport 3D and audio

    I plan to buy the samsung S27A950D (3D at 1920x1080@120)

    I wonder, if chips including a DCE4 can:
    - generate displayport 3D link data?
    - generate displayport audio?

    For the displayport 3D...
  16. VESA and external PCI-E simple and "standard" interfaces for monitors?

    We all know where external PCI-E is going.

    What's up with a VESA standard to define simple interfaces over PCI-E for monitors?
  17. Replies
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    oops... if I recall well, it was about the DCE of...

    oops... if I recall well, it was about the DCE of the southern islands chips. I cannot find the www page again!
  18. I did a bit of testing and, with a zeroed param...

    I did a bit of testing and, with a zeroed param struct, only the pixel clock field, the crtc id field and the pll_id field seem to be relevant for crtc virtual pixel clock programming.

    Am I right...
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    Well... the only interest of UVD is the W saved...

    Well... the only interest of UVD is the W saved for battery based systems.

    We should not forget the hardware programing manual of the discret dma engines too, except if it's decided to remove them...
  20. CRTC virtual pixel clock in displayport mode, and atombios SetPixelClock

    Hi,
    In displayport mode, the DCPLL defaults to 600MHz for DCE4 and 540MHz for DCE5.

    When programming the video mode for a crtc, SetPixelClock command table is used.
    What are the parameters...
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