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    Greetings! I have reviewed all open documents and found no mention of the PLL registers, which are responsible for pixelclock. For example EXT1_PPLL_POST_DIV - one of them . They are still under the NDA? But it without them not to setvideomode ... Whether documentation in the future?

  • #2
    Originally posted by OleSt View Post
    Greetings! I have reviewed all open documents and found no mention of the PLL registers, which are responsible for pixelclock. For example EXT1_PPLL_POST_DIV - one of them . They are still under the NDA? But it without them not to setvideomode ... Whether documentation in the future?
    Yes they were not included in documentation, for unknown reason (at least i don't know why) but you can find good description of them in radeonhd, or radeon even xf86-video-avivo have some basic description of what we did understand at the time we did RE.

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    • #3
      Yes, I saw them there. Just interesting, this NDA or simply forgotten to provide documentation. Thanks for your reply .

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      • #4
        Originally posted by OleSt View Post
        Yes, I saw them there. Just interesting, this NDA or simply forgotten to provide documentation. Thanks for your reply .
        They were accidentally left out of the open source documents that our internal documentation team built for release. The register information is definitely ok for release, it just got left out. The radeonhd source should provide any information you need about the bitfields. We do plan to eventually get the information out, I just haven't gotten around to it yet.

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        • #5
          Yep. In order to get the project moving more quickly we started with some already-sanitized documents which (in theory) covered all the registers needed for modesetting. The Novell developers found a number of areas missing so as each gap was discovered we collected the information and sent it across via email or a small doc for a specific set of registers. There are probably 50 of those "doc-lets" which we have to collect, clean up, review, and turn into a real document.

          My current thinking is to do that after R6xx 3D documentation is released, but if anyone has specific questions they can email us at the address on the Open GPU Documentation page at amd.com.

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          • #6
            Has written in amd. If they now will not have time, with impatience will wait for official addition to specifications .

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